mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-24 11:59:46 +09:00
5d6050fdb8
This patch adds the new Barco platinum platform. It currently includes those two boards: platinum-titanium ----------------- This is the same board as the titanium that is already supported in mainline U-Boot. But its now moved to this new platform to support multiple "flavors" of imx6 boards in one directory. Its also moved to support SPL booting. And with this we use the run-time DDR configuration of this SPL support. The board is equipped with the Micron MT41J128M16JT-125 DDR chips. We now can remove the DDR related registers tuples from the imximage.cfg file. As all this is done in the SPL at run-time. platinum-picon -------------- This board is new and based on the MX6DL with 1GiB DDR using the Micron MT41K256M16HA DDR3 chips. Its also equipped with 2 NAND chips (each 512MiB). Signed-off-by: Stefan Roese <sr@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Pieter Ronsijn <pieter.ronsijn@barco.com>
89 lines
2.6 KiB
C
89 lines
2.6 KiB
C
/*
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* Copyright (C) 2014 Stefan Roese <sr@denx.de>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _PLATINUM_H_
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#define _PLATINUM_H_
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#include <miiphy.h>
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#include <asm/arch/crm_regs.h>
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/* Defines */
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#define ECSPI1_PAD_CLK (PAD_CTL_SRE_SLOW | PAD_CTL_PUS_100K_DOWN | \
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PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \
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PAD_CTL_HYS)
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#define ECSPI2_PAD_CLK (PAD_CTL_SRE_FAST | PAD_CTL_PUS_100K_DOWN | \
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
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PAD_CTL_HYS)
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#define ECSPI_PAD_MOSI (PAD_CTL_SRE_SLOW | PAD_CTL_PUS_100K_DOWN | \
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PAD_CTL_SPEED_LOW | PAD_CTL_DSE_120ohm | \
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PAD_CTL_HYS)
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#define ECSPI_PAD_MISO (PAD_CTL_SRE_FAST | PAD_CTL_PUS_100K_DOWN | \
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PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \
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PAD_CTL_HYS)
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#define ECSPI_PAD_SS (PAD_CTL_SRE_SLOW | PAD_CTL_PUS_100K_UP | \
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PAD_CTL_SPEED_LOW | PAD_CTL_DSE_120ohm | \
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PAD_CTL_HYS)
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#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
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#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
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PAD_CTL_ODE | PAD_CTL_SRE_FAST)
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#define I2C_PAD_CTRL_SCL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \
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PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \
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PAD_CTL_ODE | PAD_CTL_SRE_SLOW)
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#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
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PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | \
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PAD_CTL_HYS)
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#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \
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PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | \
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PAD_CTL_HYS)
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#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
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#define PC_SCL MUX_PAD_CTRL(I2C_PAD_CTRL_SCL)
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/* Prototypes */
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int platinum_setup_enet(void);
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int platinum_setup_i2c(void);
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int platinum_setup_spi(void);
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int platinum_setup_uart(void);
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int platinum_phy_config(struct phy_device *phydev);
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int platinum_init_gpio(void);
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int platinum_init_usb(void);
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int platinum_init_finished(void);
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static inline void ccgr_init(void)
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{
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struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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writel(0x00C03F3F, &ccm->CCGR0);
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writel(0x0030FC03, &ccm->CCGR1);
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writel(0x0FFFC000, &ccm->CCGR2);
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writel(0x3FF00000, &ccm->CCGR3);
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writel(0xFFFFF300, &ccm->CCGR4); /* enable NAND/GPMI/BCH clks */
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writel(0x0F0000C3, &ccm->CCGR5);
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writel(0x000003FF, &ccm->CCGR6);
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}
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static inline void gpr_init(void)
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{
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struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
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/* enable AXI cache for VDOA/VPU/IPU */
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writel(0xF00000CF, &iomux->gpr[4]);
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/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
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writel(0x007F007F, &iomux->gpr[6]);
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writel(0x007F007F, &iomux->gpr[7]);
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}
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#endif /* _PLATINUM_H_ */
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