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https://github.com/brain-hackers/u-boot-brain
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5de851403b
This patch reworks the 440GX interrupt handling so that the common 4xx code can be used. The 440GX is an exception to all other 4xx variants by having the cascading interrupt vectors not on UIC0 but on a special UIC named UICB0 (UIC Base 0). With this patch now, U-Boot references the 440GX UICB0 when UIC0 is selected. And the common 4xx interrupt handling is simpler without any 440GX special cases. Also some additional cleanup to cpu/ppc4xx/interrupt.c is done. Signed-off-by: Stefan Roese <sr@denx.de>
314 lines
11 KiB
C
314 lines
11 KiB
C
/*
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* Copyright (C) 2004 PaulReynolds@lhsolutions.com
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*
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* (C) Copyright 2007
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/processor.h>
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#include <spd_sdram.h>
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#include <ppc4xx_enet.h>
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#ifdef CFG_INIT_SHOW_RESET_REG
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void show_reset_reg(void);
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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int lcd_init(void);
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int board_early_init_f (void)
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{
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unsigned long reg;
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volatile unsigned int *GpioOdr;
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volatile unsigned int *GpioTcr;
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volatile unsigned int *GpioOr;
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/*-------------------------------------------------------------------------+
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| Initialize EBC CONFIG
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+-------------------------------------------------------------------------*/
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mtebc(xbcfg, EBC_CFG_LE_UNLOCK |
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EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK |
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EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS |
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EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_DEFAULT |
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EBC_CFG_PME_DISABLE | EBC_CFG_PR_32);
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/*-------------------------------------------------------------------------+
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| 64MB FLASH. Initialize bank 0 with default values.
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+-------------------------------------------------------------------------*/
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mtebc(pb0ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(15) |
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EBC_BXAP_BCE_DISABLE |
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EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_OEN_ENCODE(1) |
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EBC_BXAP_WBN_ENCODE(1) | EBC_BXAP_WBF_ENCODE(1) |
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EBC_BXAP_TH_ENCODE(3) | EBC_BXAP_RE_DISABLED |
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EBC_BXAP_BEM_WRITEONLY |
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EBC_BXAP_PEN_DISABLED);
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mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CFG_FLASH_BASE) |
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EBC_BXCR_BS_64MB | EBC_BXCR_BU_RW|EBC_BXCR_BW_32BIT);
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/*-------------------------------------------------------------------------+
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| FPGA. Initialize bank 1 with default values.
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+-------------------------------------------------------------------------*/
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mtebc(pb1ap, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(5) |
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EBC_BXAP_BCE_DISABLE |
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EBC_BXAP_CSN_ENCODE(1) | EBC_BXAP_OEN_ENCODE(1) |
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EBC_BXAP_WBN_ENCODE(1) | EBC_BXAP_WBF_ENCODE(1) |
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EBC_BXAP_TH_ENCODE(3) | EBC_BXAP_RE_DISABLED |
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EBC_BXAP_BEM_WRITEONLY |
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EBC_BXAP_PEN_DISABLED);
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mtebc(pb1cr, EBC_BXCR_BAS_ENCODE(0x41000000) |
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EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
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/*-------------------------------------------------------------------------+
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| LCM. Initialize bank 2 with default values.
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+-------------------------------------------------------------------------*/
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mtebc(pb2ap, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(64) |
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EBC_BXAP_BCE_DISABLE |
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EBC_BXAP_CSN_ENCODE(3) | EBC_BXAP_OEN_ENCODE(3) |
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EBC_BXAP_WBN_ENCODE(3) | EBC_BXAP_WBF_ENCODE(3) |
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EBC_BXAP_TH_ENCODE(7) | EBC_BXAP_RE_DISABLED |
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EBC_BXAP_BEM_WRITEONLY |
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EBC_BXAP_PEN_DISABLED);
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mtebc(pb2cr, EBC_BXCR_BAS_ENCODE(0x42000000) |
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EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
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/*-------------------------------------------------------------------------+
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| TMP. Initialize bank 3 with default values.
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+-------------------------------------------------------------------------*/
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mtebc(pb3ap, EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(128) |
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EBC_BXAP_BCE_DISABLE |
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EBC_BXAP_CSN_ENCODE(3) | EBC_BXAP_OEN_ENCODE(3) |
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EBC_BXAP_WBN_ENCODE(3) | EBC_BXAP_WBF_ENCODE(3) |
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EBC_BXAP_TH_ENCODE(7) | EBC_BXAP_RE_DISABLED |
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EBC_BXAP_BEM_WRITEONLY |
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EBC_BXAP_PEN_DISABLED);
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mtebc(pb3cr, EBC_BXCR_BAS_ENCODE(0x48000000) |
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EBC_BXCR_BS_64MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT);
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/*-------------------------------------------------------------------------+
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| Connector 4~7. Initialize bank 3~ 7 with default values.
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+-------------------------------------------------------------------------*/
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mtebc(pb4ap,0);
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mtebc(pb4cr,0);
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mtebc(pb5ap,0);
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mtebc(pb5cr,0);
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mtebc(pb6ap,0);
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mtebc(pb6cr,0);
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mtebc(pb7ap,0);
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mtebc(pb7cr,0);
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/*--------------------------------------------------------------------
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* Setup the interrupt controller polarities, triggers, etc.
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*-------------------------------------------------------------------*/
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/*
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* Because of the interrupt handling rework to handle 440GX interrupts
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* with the common code, we needed to change names of the UIC registers.
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* Here the new relationship:
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*
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* U-Boot name 440GX name
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* -----------------------
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* UIC0 UICB0
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* UIC1 UIC0
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* UIC2 UIC1
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* UIC3 UIC2
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*/
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mtdcr (uic1sr, 0xffffffff); /* clear all */
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mtdcr (uic1er, 0x00000000); /* disable all */
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mtdcr (uic1cr, 0x00000009); /* SMI & UIC1 crit are critical */
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mtdcr (uic1pr, 0xfffffe13); /* per ref-board manual */
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mtdcr (uic1tr, 0x01c00008); /* per ref-board manual */
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mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */
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mtdcr (uic1sr, 0xffffffff); /* clear all */
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mtdcr (uic2sr, 0xffffffff); /* clear all */
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mtdcr (uic2er, 0x00000000); /* disable all */
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mtdcr (uic2cr, 0x00000000); /* all non-critical */
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mtdcr (uic2pr, 0xffffe0ff); /* per ref-board manual */
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mtdcr (uic2tr, 0x00ffc000); /* per ref-board manual */
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mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */
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mtdcr (uic2sr, 0xffffffff); /* clear all */
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mtdcr (uic3sr, 0xffffffff); /* clear all */
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mtdcr (uic3er, 0x00000000); /* disable all */
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mtdcr (uic3cr, 0x00000000); /* all non-critical */
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mtdcr (uic3pr, 0xffffffff); /* per ref-board manual */
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mtdcr (uic3tr, 0x00ff8c0f); /* per ref-board manual */
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mtdcr (uic3vr, 0x00000001); /* int31 highest, base=0x000 */
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mtdcr (uic3sr, 0xffffffff); /* clear all */
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mtdcr (uic0sr, 0xfc000000); /* clear all */
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mtdcr (uic0er, 0x00000000); /* disable all */
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mtdcr (uic0cr, 0x00000000); /* all non-critical */
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mtdcr (uic0pr, 0xfc000000); /* */
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mtdcr (uic0tr, 0x00000000); /* */
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mtdcr (uic0vr, 0x00000001); /* */
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/* Enable two GPIO 10~11 and TraceA signal */
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mfsdr(sdr_pfc0,reg);
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reg |= 0x00300000;
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mtsdr(sdr_pfc0,reg);
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mfsdr(sdr_pfc1,reg);
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reg |= 0x00100000;
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mtsdr(sdr_pfc1,reg);
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/* Set GPIO 10 and 11 as output */
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GpioOdr = (volatile unsigned int*)(CFG_PERIPHERAL_BASE+0x718);
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GpioTcr = (volatile unsigned int*)(CFG_PERIPHERAL_BASE+0x704);
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GpioOr = (volatile unsigned int*)(CFG_PERIPHERAL_BASE+0x700);
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*GpioOdr &= ~(0x00300000);
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*GpioTcr |= 0x00300000;
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*GpioOr |= 0x00300000;
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return 0;
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}
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int misc_init_r(void)
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{
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lcd_init();
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return 0;
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}
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int checkboard (void)
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{
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char *s = getenv ("serial#");
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printf ("Board: Taishan - AMCC PPC440GX Evaluation Board");
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if (s != NULL) {
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puts (", serial# ");
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puts (s);
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}
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putc ('\n');
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#ifdef CFG_INIT_SHOW_RESET_REG
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show_reset_reg();
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#endif
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return (0);
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}
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/*************************************************************************
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* pci_pre_init
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*
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* This routine is called just prior to registering the hose and gives
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* the board the opportunity to check things. Returning a value of zero
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* indicates that things are bad & PCI initialization should be aborted.
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*
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* Different boards may wish to customize the pci controller structure
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* (add regions, override default access routines, etc) or perform
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* certain pre-initialization actions.
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*
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************************************************************************/
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#if defined(CONFIG_PCI)
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int pci_pre_init(struct pci_controller * hose )
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{
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unsigned long strap;
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/*--------------------------------------------------------------------------+
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* The ocotea board is always configured as the host & requires the
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* PCI arbiter to be enabled.
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*--------------------------------------------------------------------------*/
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mfsdr(sdr_sdstp1, strap);
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if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ){
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printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap);
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return 0;
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}
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return 1;
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}
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#endif /* defined(CONFIG_PCI) */
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/*************************************************************************
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* pci_target_init
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*
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* The bootstrap configuration provides default settings for the pci
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* inbound map (PIM). But the bootstrap config choices are limited and
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* may not be sufficient for a given board.
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*
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************************************************************************/
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#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
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void pci_target_init(struct pci_controller * hose )
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{
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/*--------------------------------------------------------------------------+
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* Disable everything
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*--------------------------------------------------------------------------*/
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out32r( PCIX0_PIM0SA, 0 ); /* disable */
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out32r( PCIX0_PIM1SA, 0 ); /* disable */
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out32r( PCIX0_PIM2SA, 0 ); /* disable */
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out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
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/*--------------------------------------------------------------------------+
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* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
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* options to not support sizes such as 128/256 MB.
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*--------------------------------------------------------------------------*/
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out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
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out32r( PCIX0_PIM0LAH, 0 );
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out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
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out32r( PCIX0_BAR0, 0 );
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/*--------------------------------------------------------------------------+
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* Program the board's subsystem id/vendor id
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*--------------------------------------------------------------------------*/
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out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
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out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
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out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
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}
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#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
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/*************************************************************************
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* is_pci_host
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*
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* This routine is called to determine if a pci scan should be
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* performed. With various hardware environments (especially cPCI and
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* PPMC) it's insufficient to depend on the state of the arbiter enable
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* bit in the strap register, or generic host/adapter assumptions.
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*
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* Rather than hard-code a bad assumption in the general 440 code, the
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* 440 pci code requires the board to decide at runtime.
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*
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* Return 0 for adapter mode, non-zero for host (monarch) mode.
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*
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*
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************************************************************************/
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#if defined(CONFIG_PCI)
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int is_pci_host(struct pci_controller *hose)
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{
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/* The ocotea board is always configured as host. */
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return(1);
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}
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#endif /* defined(CONFIG_PCI) */
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#ifdef CONFIG_POST
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/*
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* Returns 1 if keys pressed to start the power-on long-running tests
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* Called from board_init_f().
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*/
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int post_hotkeys_pressed(void)
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{
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return (ctrlc());
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}
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#endif
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