mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-14 22:23:56 +09:00
325 lines
8.4 KiB
C
325 lines
8.4 KiB
C
/*
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* (C) Copyright 2000, 2001
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* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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/*
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* FPGA support
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*/
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#include <common.h>
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#include <command.h>
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#if (CONFIG_COMMANDS & CFG_CMD_NET)
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#include <net.h>
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#endif
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#include <fpga.h>
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#include <malloc.h>
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#if 0
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#define FPGA_DEBUG
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#endif
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#ifdef FPGA_DEBUG
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#define PRINTF(fmt,args...) printf (fmt ,##args)
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#else
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#define PRINTF(fmt,args...)
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#endif
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#if defined (CONFIG_FPGA) && ( CONFIG_COMMANDS & CFG_CMD_FPGA )
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/* Local functions */
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static void fpga_usage (cmd_tbl_t * cmdtp);
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static int fpga_get_op (char *opstr);
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/* Local defines */
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#define FPGA_NONE -1
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#define FPGA_INFO 0
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#define FPGA_LOAD 1
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#define FPGA_LOADB 2
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#define FPGA_DUMP 3
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#define FPGA_LOADMK 4
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/* Convert bitstream data and load into the fpga */
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int fpga_loadbitstream(unsigned long dev, char* fpgadata, size_t size)
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{
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unsigned int length;
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unsigned char* swapdata;
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unsigned int swapsize;
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char buffer[80];
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unsigned char *ptr;
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unsigned char *dataptr;
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unsigned char data;
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unsigned int i;
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int rc;
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dataptr = (unsigned char *)fpgadata;
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#if CFG_FPGA_XILINX
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/* skip the first bytes of the bitsteam, their meaning is unknown */
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length = (*dataptr << 8) + *(dataptr+1);
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dataptr+=2;
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dataptr+=length;
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/* get design name (identifier, length, string) */
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length = (*dataptr << 8) + *(dataptr+1);
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dataptr+=2;
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if (*dataptr++ != 0x61) {
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PRINTF ("%s: Design name identifier not recognized in bitstream\n",
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__FUNCTION__ );
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return FPGA_FAIL;
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}
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length = (*dataptr << 8) + *(dataptr+1);
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dataptr+=2;
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for(i=0;i<length;i++)
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buffer[i]=*dataptr++;
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printf(" design filename = \"%s\"\n", buffer);
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/* get part number (identifier, length, string) */
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if (*dataptr++ != 0x62) {
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printf("%s: Part number identifier not recognized in bitstream\n",
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__FUNCTION__ );
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return FPGA_FAIL;
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}
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length = (*dataptr << 8) + *(dataptr+1);
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dataptr+=2;
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for(i=0;i<length;i++)
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buffer[i]=*dataptr++;
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printf(" part number = \"%s\"\n", buffer);
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/* get date (identifier, length, string) */
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if (*dataptr++ != 0x63) {
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printf("%s: Date identifier not recognized in bitstream\n",
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__FUNCTION__);
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return FPGA_FAIL;
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}
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length = (*dataptr << 8) + *(dataptr+1);
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dataptr+=2;
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for(i=0;i<length;i++)
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buffer[i]=*dataptr++;
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printf(" date = \"%s\"\n", buffer);
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/* get time (identifier, length, string) */
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if (*dataptr++ != 0x64) {
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printf("%s: Time identifier not recognized in bitstream\n",__FUNCTION__);
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return FPGA_FAIL;
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}
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length = (*dataptr << 8) + *(dataptr+1);
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dataptr+=2;
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for(i=0;i<length;i++)
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buffer[i]=*dataptr++;
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printf(" time = \"%s\"\n", buffer);
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/* get fpga data length (identifier, length) */
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if (*dataptr++ != 0x65) {
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printf("%s: Data length identifier not recognized in bitstream\n",
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__FUNCTION__);
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return FPGA_FAIL;
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}
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swapsize = ((unsigned int) *dataptr <<24) +
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((unsigned int) *(dataptr+1) <<16) +
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((unsigned int) *(dataptr+2) <<8 ) +
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((unsigned int) *(dataptr+3) ) ;
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dataptr+=4;
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printf(" bytes in bitstream = %d\n", swapsize);
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/* check consistency of length obtained */
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if (swapsize >= size) {
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printf("%s: Could not find right length of data in bitstream\n",
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__FUNCTION__);
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return FPGA_FAIL;
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}
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/* allocate memory */
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swapdata = (unsigned char *)malloc(swapsize);
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if (swapdata == NULL) {
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printf("%s: Could not allocate %d bytes memory !\n",
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__FUNCTION__, swapsize);
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return FPGA_FAIL;
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}
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/* read data into memory and swap bits */
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ptr = swapdata;
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for (i = 0; i < swapsize; i++) {
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data = 0x00;
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data |= (*dataptr & 0x01) << 7;
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data |= (*dataptr & 0x02) << 5;
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data |= (*dataptr & 0x04) << 3;
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data |= (*dataptr & 0x08) << 1;
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data |= (*dataptr & 0x10) >> 1;
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data |= (*dataptr & 0x20) >> 3;
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data |= (*dataptr & 0x40) >> 5;
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data |= (*dataptr & 0x80) >> 7;
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*ptr++ = data;
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dataptr++;
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}
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rc = fpga_load(dev, swapdata, swapsize);
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free(swapdata);
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return rc;
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#else
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printf("Bitstream support only for Xilinx devices\n");
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return FPGA_FAIL;
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#endif
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}
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/* ------------------------------------------------------------------------- */
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/* command form:
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* fpga <op> <device number> <data addr> <datasize>
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* where op is 'load', 'dump', or 'info'
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* If there is no device number field, the fpga environment variable is used.
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* If there is no data addr field, the fpgadata environment variable is used.
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* The info command requires no data address field.
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*/
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int do_fpga (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
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{
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int op, dev = FPGA_INVALID_DEVICE;
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size_t data_size = 0;
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void *fpga_data = NULL;
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char *devstr = getenv ("fpga");
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char *datastr = getenv ("fpgadata");
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int rc = FPGA_FAIL;
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if (devstr)
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dev = (int) simple_strtoul (devstr, NULL, 16);
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if (datastr)
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fpga_data = (void *) simple_strtoul (datastr, NULL, 16);
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switch (argc) {
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case 5: /* fpga <op> <dev> <data> <datasize> */
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data_size = simple_strtoul (argv[4], NULL, 16);
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case 4: /* fpga <op> <dev> <data> */
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fpga_data = (void *) simple_strtoul (argv[3], NULL, 16);
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PRINTF ("%s: fpga_data = 0x%x\n", __FUNCTION__, (uint) fpga_data);
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case 3: /* fpga <op> <dev | data addr> */
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dev = (int) simple_strtoul (argv[2], NULL, 16);
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PRINTF ("%s: device = %d\n", __FUNCTION__, dev);
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/* FIXME - this is a really weak test */
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if ((argc == 3) && (dev > fpga_count ())) { /* must be buffer ptr */
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PRINTF ("%s: Assuming buffer pointer in arg 3\n",
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__FUNCTION__);
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fpga_data = (void *) dev;
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PRINTF ("%s: fpga_data = 0x%x\n",
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__FUNCTION__, (uint) fpga_data);
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dev = FPGA_INVALID_DEVICE; /* reset device num */
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}
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case 2: /* fpga <op> */
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op = (int) fpga_get_op (argv[1]);
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break;
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default:
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PRINTF ("%s: Too many or too few args (%d)\n",
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__FUNCTION__, argc);
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op = FPGA_NONE; /* force usage display */
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break;
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}
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switch (op) {
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case FPGA_NONE:
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fpga_usage (cmdtp);
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break;
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case FPGA_INFO:
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rc = fpga_info (dev);
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break;
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case FPGA_LOAD:
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rc = fpga_load (dev, fpga_data, data_size);
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break;
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case FPGA_LOADB:
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rc = fpga_loadbitstream(dev, fpga_data, data_size);
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break;
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case FPGA_LOADMK:
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{
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image_header_t header;
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image_header_t *hdr = &header;
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ulong data;
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memmove (&header, (char *)fpga_data, sizeof(image_header_t));
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if (ntohl(hdr->ih_magic) != IH_MAGIC) {
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puts ("Bad Magic Number\n");
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return 1;
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}
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data = ((ulong)fpga_data + sizeof(image_header_t));
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data_size = ntohl(hdr->ih_size);
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rc = fpga_load (dev, (void *)data, data_size);
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}
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break;
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case FPGA_DUMP:
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rc = fpga_dump (dev, fpga_data, data_size);
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break;
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default:
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printf ("Unknown operation\n");
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fpga_usage (cmdtp);
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break;
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}
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return (rc);
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}
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static void fpga_usage (cmd_tbl_t * cmdtp)
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{
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printf ("Usage:\n%s\n", cmdtp->usage);
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}
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/*
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* Map op to supported operations. We don't use a table since we
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* would just have to relocate it from flash anyway.
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*/
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static int fpga_get_op (char *opstr)
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{
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int op = FPGA_NONE;
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if (!strcmp ("info", opstr)) {
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op = FPGA_INFO;
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} else if (!strcmp ("loadb", opstr)) {
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op = FPGA_LOADB;
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} else if (!strcmp ("load", opstr)) {
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op = FPGA_LOAD;
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} else if (!strcmp ("loadmk", opstr)) {
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op = FPGA_LOADMK;
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} else if (!strcmp ("dump", opstr)) {
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op = FPGA_DUMP;
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}
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if (op == FPGA_NONE) {
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printf ("Unknown fpga operation \"%s\"\n", opstr);
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}
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return op;
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}
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U_BOOT_CMD (fpga, 6, 1, do_fpga,
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"fpga - loadable FPGA image support\n",
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"fpga [operation type] [device number] [image address] [image size]\n"
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"fpga operations:\n"
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"\tinfo\tlist known device information\n"
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"\tload\tLoad device from memory buffer\n"
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"\tloadb\tLoad device from bitstream buffer (Xilinx devices only)\n"
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"\tloadmk\tLoad device generated with mkimage\n"
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"\tdump\tLoad device to memory buffer\n");
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#endif /* CONFIG_FPGA && CONFIG_COMMANDS & CFG_CMD_FPGA */
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