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https://github.com/brain-hackers/u-boot-brain
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![Dylan Hung](/assets/img/avatar_default.png)
to improve the maintainability. It is more easier to modify and add configurations of the driver in the centralized ram driver directory. Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
440 lines
11 KiB
C
440 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2012-2020 ASPEED Technology Inc.
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*
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* Copyright 2016 Google, Inc
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*/
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#include <common.h>
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#include <clk.h>
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#include <dm.h>
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#include <errno.h>
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#include <log.h>
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#include <ram.h>
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#include <regmap.h>
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#include <reset.h>
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#include <asm/io.h>
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#include <asm/arch/scu_ast2500.h>
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#include <asm/arch/sdram_ast2500.h>
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#include <asm/arch/wdt.h>
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#include <linux/err.h>
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#include <linux/kernel.h>
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#include <dt-bindings/clock/aspeed-clock.h>
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/* These configuration parameters are taken from Aspeed SDK */
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#define DDR4_MR46_MODE 0x08000000
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#define DDR4_MR5_MODE 0x400
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#define DDR4_MR13_MODE 0x101
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#define DDR4_MR02_MODE 0x410
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#define DDR4_TRFC 0x45457188
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#define PHY_CFG_SIZE 15
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static const u32 ddr4_ac_timing[3] = {0x63604e37, 0xe97afa99, 0x00019000};
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static const struct {
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u32 index[PHY_CFG_SIZE];
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u32 value[PHY_CFG_SIZE];
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} ddr4_phy_config = {
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.index = {0, 1, 3, 4, 5, 56, 57, 58, 59, 60, 61, 62, 36, 49, 50},
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.value = {
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0x42492aae, 0x09002000, 0x55e00b0b, 0x20000000, 0x24,
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0x03002900, 0x0e0000a0, 0x000e001c, 0x35b8c106, 0x08080607,
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0x9b000900, 0x0e400a00, 0x00100008, 0x3c183c3c, 0x00631e0e,
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},
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};
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#define SDRAM_MAX_SIZE (1024 * 1024 * 1024)
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#define SDRAM_MIN_SIZE (128 * 1024 * 1024)
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* Bandwidth configuration parameters for different SDRAM requests.
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* These are hardcoded settings taken from Aspeed SDK.
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*/
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static const u32 ddr_max_grant_params[4] = {
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0x88448844, 0x24422288, 0x22222222, 0x22222222
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};
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/*
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* These registers are not documented by Aspeed at all.
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* All writes and reads are taken pretty much as is from SDK.
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*/
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struct ast2500_ddr_phy {
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u32 phy[117];
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};
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struct dram_info {
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struct ram_info info;
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struct clk ddr_clk;
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struct ast2500_sdrammc_regs *regs;
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struct ast2500_scu *scu;
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struct ast2500_ddr_phy *phy;
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ulong clock_rate;
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};
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static int ast2500_sdrammc_init_phy(struct ast2500_ddr_phy *phy)
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{
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writel(0, &phy->phy[2]);
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writel(0, &phy->phy[6]);
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writel(0, &phy->phy[8]);
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writel(0, &phy->phy[10]);
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writel(0, &phy->phy[12]);
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writel(0, &phy->phy[42]);
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writel(0, &phy->phy[44]);
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writel(0x86000000, &phy->phy[16]);
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writel(0x00008600, &phy->phy[17]);
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writel(0x80000000, &phy->phy[18]);
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writel(0x80808080, &phy->phy[19]);
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return 0;
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}
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static void ast2500_ddr_phy_init_process(struct dram_info *info)
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{
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struct ast2500_sdrammc_regs *regs = info->regs;
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writel(0, ®s->phy_ctrl[0]);
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writel(0x4040, &info->phy->phy[51]);
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writel(SDRAM_PHYCTRL0_NRST | SDRAM_PHYCTRL0_INIT, ®s->phy_ctrl[0]);
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while ((readl(®s->phy_ctrl[0]) & SDRAM_PHYCTRL0_INIT))
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;
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writel(SDRAM_PHYCTRL0_NRST | SDRAM_PHYCTRL0_AUTO_UPDATE,
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®s->phy_ctrl[0]);
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}
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static void ast2500_sdrammc_set_vref(struct dram_info *info, u32 vref)
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{
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writel(0, &info->regs->phy_ctrl[0]);
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writel((vref << 8) | 0x6, &info->phy->phy[48]);
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ast2500_ddr_phy_init_process(info);
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}
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static int ast2500_ddr_cbr_test(struct dram_info *info)
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{
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struct ast2500_sdrammc_regs *regs = info->regs;
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int i;
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const u32 test_params = SDRAM_TEST_EN
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| SDRAM_TEST_ERRSTOP
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| SDRAM_TEST_TWO_MODES;
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int ret = 0;
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writel((1 << SDRAM_REFRESH_CYCLES_SHIFT) |
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(0x5c << SDRAM_REFRESH_PERIOD_SHIFT), ®s->refresh_timing);
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writel((0xfff << SDRAM_TEST_LEN_SHIFT), ®s->test_addr);
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writel(0xff00ff00, ®s->test_init_val);
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writel(SDRAM_TEST_EN | (SDRAM_TEST_MODE_RW << SDRAM_TEST_MODE_SHIFT) |
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SDRAM_TEST_ERRSTOP, ®s->ecc_test_ctrl);
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while (!(readl(®s->ecc_test_ctrl) & SDRAM_TEST_DONE))
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;
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if (readl(®s->ecc_test_ctrl) & SDRAM_TEST_FAIL) {
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ret = -EIO;
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} else {
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for (i = 0; i <= SDRAM_TEST_GEN_MODE_MASK; ++i) {
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writel((i << SDRAM_TEST_GEN_MODE_SHIFT) | test_params,
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®s->ecc_test_ctrl);
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while (!(readl(®s->ecc_test_ctrl) & SDRAM_TEST_DONE))
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;
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if (readl(®s->ecc_test_ctrl) & SDRAM_TEST_FAIL) {
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ret = -EIO;
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break;
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}
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}
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}
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writel(0, ®s->refresh_timing);
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writel(0, ®s->ecc_test_ctrl);
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return ret;
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}
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static int ast2500_sdrammc_ddr4_calibrate_vref(struct dram_info *info)
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{
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int i;
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int vref_min = 0xff;
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int vref_max = 0;
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int range_size = 0;
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for (i = 1; i < 0x40; ++i) {
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int res;
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ast2500_sdrammc_set_vref(info, i);
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res = ast2500_ddr_cbr_test(info);
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if (res < 0) {
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if (range_size > 0)
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break;
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} else {
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++range_size;
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vref_min = min(vref_min, i);
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vref_max = max(vref_max, i);
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}
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}
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/* Pick average setting */
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ast2500_sdrammc_set_vref(info, (vref_min + vref_max + 1) / 2);
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return 0;
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}
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static size_t ast2500_sdrammc_get_vga_mem_size(struct dram_info *info)
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{
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size_t vga_mem_size_base = 8 * 1024 * 1024;
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u32 vga_hwconf = (readl(&info->scu->hwstrap) & SCU_HWSTRAP_VGAMEM_MASK)
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>> SCU_HWSTRAP_VGAMEM_SHIFT;
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return vga_mem_size_base << vga_hwconf;
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}
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/*
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* Find out RAM size and save it in dram_info
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*
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* The procedure is taken from Aspeed SDK
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*/
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static void ast2500_sdrammc_calc_size(struct dram_info *info)
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{
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/* The controller supports 128/256/512/1024 MB ram */
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size_t ram_size = SDRAM_MIN_SIZE;
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const int write_test_offset = 0x100000;
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u32 test_pattern = 0xdeadbeef;
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u32 cap_param = SDRAM_CONF_CAP_1024M;
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u32 refresh_timing_param = DDR4_TRFC;
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const u32 write_addr_base = CONFIG_SYS_SDRAM_BASE + write_test_offset;
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for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE;
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ram_size >>= 1) {
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writel(test_pattern, write_addr_base + (ram_size >> 1));
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test_pattern = (test_pattern >> 4) | (test_pattern << 28);
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}
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/* One last write to overwrite all wrapped values */
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writel(test_pattern, write_addr_base);
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/* Reset the pattern and see which value was really written */
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test_pattern = 0xdeadbeef;
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for (ram_size = SDRAM_MAX_SIZE; ram_size > SDRAM_MIN_SIZE;
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ram_size >>= 1) {
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if (readl(write_addr_base + (ram_size >> 1)) == test_pattern)
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break;
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--cap_param;
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refresh_timing_param >>= 8;
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test_pattern = (test_pattern >> 4) | (test_pattern << 28);
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}
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clrsetbits_le32(&info->regs->ac_timing[1],
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(SDRAM_AC_TRFC_MASK << SDRAM_AC_TRFC_SHIFT),
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((refresh_timing_param & SDRAM_AC_TRFC_MASK)
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<< SDRAM_AC_TRFC_SHIFT));
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info->info.base = CONFIG_SYS_SDRAM_BASE;
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info->info.size = ram_size - ast2500_sdrammc_get_vga_mem_size(info);
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clrsetbits_le32(&info->regs->config,
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(SDRAM_CONF_CAP_MASK << SDRAM_CONF_CAP_SHIFT),
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((cap_param & SDRAM_CONF_CAP_MASK)
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<< SDRAM_CONF_CAP_SHIFT));
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}
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static int ast2500_sdrammc_init_ddr4(struct dram_info *info)
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{
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int i;
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const u32 power_control = SDRAM_PCR_CKE_EN
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| (1 << SDRAM_PCR_CKE_DELAY_SHIFT)
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| (2 << SDRAM_PCR_TCKE_PW_SHIFT)
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| SDRAM_PCR_RESETN_DIS
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| SDRAM_PCR_RGAP_CTRL_EN | SDRAM_PCR_ODT_EN | SDRAM_PCR_ODT_EXT_EN;
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const u32 conf = (SDRAM_CONF_CAP_1024M << SDRAM_CONF_CAP_SHIFT)
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#ifdef CONFIG_DUALX8_RAM
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| SDRAM_CONF_DUALX8
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#endif
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| SDRAM_CONF_SCRAMBLE | SDRAM_CONF_SCRAMBLE_PAT2 | SDRAM_CONF_DDR4;
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int ret;
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writel(conf, &info->regs->config);
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for (i = 0; i < ARRAY_SIZE(ddr4_ac_timing); ++i)
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writel(ddr4_ac_timing[i], &info->regs->ac_timing[i]);
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writel(DDR4_MR46_MODE, &info->regs->mr46_mode_setting);
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writel(DDR4_MR5_MODE, &info->regs->mr5_mode_setting);
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writel(DDR4_MR02_MODE, &info->regs->mr02_mode_setting);
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writel(DDR4_MR13_MODE, &info->regs->mr13_mode_setting);
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for (i = 0; i < PHY_CFG_SIZE; ++i) {
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writel(ddr4_phy_config.value[i],
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&info->phy->phy[ddr4_phy_config.index[i]]);
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}
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writel(power_control, &info->regs->power_control);
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ast2500_ddr_phy_init_process(info);
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ret = ast2500_sdrammc_ddr4_calibrate_vref(info);
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if (ret < 0) {
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debug("Vref calibration failed!\n");
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return ret;
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}
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writel((1 << SDRAM_REFRESH_CYCLES_SHIFT)
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| SDRAM_REFRESH_ZQCS_EN | (0x2f << SDRAM_REFRESH_PERIOD_SHIFT),
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&info->regs->refresh_timing);
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setbits_le32(&info->regs->power_control,
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SDRAM_PCR_AUTOPWRDN_EN | SDRAM_PCR_ODT_AUTO_ON);
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ast2500_sdrammc_calc_size(info);
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setbits_le32(&info->regs->config, SDRAM_CONF_CACHE_INIT_EN);
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while (!(readl(&info->regs->config) & SDRAM_CONF_CACHE_INIT_DONE))
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;
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setbits_le32(&info->regs->config, SDRAM_CONF_CACHE_EN);
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writel(SDRAM_MISC_DDR4_TREFRESH, &info->regs->misc_control);
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/* Enable all requests except video & display */
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writel(SDRAM_REQ_USB20_EHCI1
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| SDRAM_REQ_USB20_EHCI2
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| SDRAM_REQ_CPU
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| SDRAM_REQ_AHB2
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| SDRAM_REQ_AHB
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| SDRAM_REQ_MAC0
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| SDRAM_REQ_MAC1
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| SDRAM_REQ_PCIE
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| SDRAM_REQ_XDMA
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| SDRAM_REQ_ENCRYPTION
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| SDRAM_REQ_VIDEO_FLAG
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| SDRAM_REQ_VIDEO_LOW_PRI_WRITE
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| SDRAM_REQ_2D_RW
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| SDRAM_REQ_MEMCHECK, &info->regs->req_limit_mask);
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return 0;
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}
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static void ast2500_sdrammc_unlock(struct dram_info *info)
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{
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writel(SDRAM_UNLOCK_KEY, &info->regs->protection_key);
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while (!readl(&info->regs->protection_key))
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;
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}
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static void ast2500_sdrammc_lock(struct dram_info *info)
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{
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writel(~SDRAM_UNLOCK_KEY, &info->regs->protection_key);
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while (readl(&info->regs->protection_key))
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;
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}
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static int ast2500_sdrammc_probe(struct udevice *dev)
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{
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struct reset_ctl reset_ctl;
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struct dram_info *priv = (struct dram_info *)dev_get_priv(dev);
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struct ast2500_sdrammc_regs *regs = priv->regs;
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int i;
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int ret = clk_get_by_index(dev, 0, &priv->ddr_clk);
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if (ret) {
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debug("DDR:No CLK\n");
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return ret;
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}
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priv->scu = ast_get_scu();
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if (IS_ERR(priv->scu)) {
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debug("%s(): can't get SCU\n", __func__);
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return PTR_ERR(priv->scu);
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}
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clk_set_rate(&priv->ddr_clk, priv->clock_rate);
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ret = reset_get_by_index(dev, 0, &reset_ctl);
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if (ret) {
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debug("%s(): Failed to get reset signal\n", __func__);
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return ret;
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}
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ret = reset_assert(&reset_ctl);
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if (ret) {
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debug("%s(): SDRAM reset failed: %u\n", __func__, ret);
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return ret;
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}
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ast2500_sdrammc_unlock(priv);
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writel(SDRAM_PCR_MREQI_DIS | SDRAM_PCR_RESETN_DIS,
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®s->power_control);
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writel(SDRAM_VIDEO_UNLOCK_KEY, ®s->gm_protection_key);
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/* Mask all requests except CPU and AHB during PHY init */
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writel(~(SDRAM_REQ_CPU | SDRAM_REQ_AHB), ®s->req_limit_mask);
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for (i = 0; i < ARRAY_SIZE(ddr_max_grant_params); ++i)
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writel(ddr_max_grant_params[i], ®s->max_grant_len[i]);
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setbits_le32(®s->intr_ctrl, SDRAM_ICR_RESET_ALL);
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ast2500_sdrammc_init_phy(priv->phy);
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if (readl(&priv->scu->hwstrap) & SCU_HWSTRAP_DDR4) {
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ast2500_sdrammc_init_ddr4(priv);
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} else {
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debug("Unsupported DRAM3\n");
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return -EINVAL;
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}
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clrbits_le32(®s->intr_ctrl, SDRAM_ICR_RESET_ALL);
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ast2500_sdrammc_lock(priv);
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return 0;
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}
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static int ast2500_sdrammc_ofdata_to_platdata(struct udevice *dev)
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{
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struct dram_info *priv = dev_get_priv(dev);
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struct regmap *map;
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int ret;
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ret = regmap_init_mem(dev_ofnode(dev), &map);
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if (ret)
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return ret;
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priv->regs = regmap_get_range(map, 0);
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priv->phy = regmap_get_range(map, 1);
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priv->clock_rate = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
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"clock-frequency", 0);
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if (!priv->clock_rate) {
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debug("DDR Clock Rate not defined\n");
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return -EINVAL;
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}
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return 0;
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}
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static int ast2500_sdrammc_get_info(struct udevice *dev, struct ram_info *info)
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{
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struct dram_info *priv = dev_get_priv(dev);
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*info = priv->info;
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return 0;
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}
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static struct ram_ops ast2500_sdrammc_ops = {
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.get_info = ast2500_sdrammc_get_info,
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};
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static const struct udevice_id ast2500_sdrammc_ids[] = {
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{ .compatible = "aspeed,ast2500-sdrammc" },
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{ }
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};
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U_BOOT_DRIVER(sdrammc_ast2500) = {
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.name = "aspeed_ast2500_sdrammc",
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.id = UCLASS_RAM,
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.of_match = ast2500_sdrammc_ids,
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.ops = &ast2500_sdrammc_ops,
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.ofdata_to_platdata = ast2500_sdrammc_ofdata_to_platdata,
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.probe = ast2500_sdrammc_probe,
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.priv_auto_alloc_size = sizeof(struct dram_info),
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};
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