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https://github.com/brain-hackers/u-boot-brain
synced 2024-08-18 16:08:53 +09:00
![Rajeshwari S Shinde](/assets/img/avatar_default.png)
This patch corrects the divider value written to CLKDIV register. Since SDCLKIN is divided inside controller by the DIVRATIO value set in the CLKSEL register, we need to use the same output clock value to calculate the CLKDIV value. as per user manual: cclk_in = SDCLKIN / (DIVRATIO + 1) Input parameter to mmc_clk is changed to dwmci_host, since we need the same to read DWMCI_CLKSEL register. This improves the read timing values for channel 0 on SMDK5250 from 0.288sec to 0.144sec Signed-off-by: Rajeshwari S Shinde <rajeshwari.s@samsung.com> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Pantelis Antoniou <panto@antoniou-consulting.com>
384 lines
8.4 KiB
C
384 lines
8.4 KiB
C
/*
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* (C) Copyright 2012 SAMSUNG Electronics
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* Jaehoon Chung <jh80.chung@samsung.com>
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* Rajeshawari Shinde <rajeshwari.s@samsung.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <bouncebuf.h>
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#include <common.h>
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#include <malloc.h>
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#include <mmc.h>
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#include <dwmmc.h>
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#include <asm-generic/errno.h>
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#define PAGE_SIZE 4096
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static int dwmci_wait_reset(struct dwmci_host *host, u32 value)
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{
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unsigned long timeout = 1000;
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u32 ctrl;
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dwmci_writel(host, DWMCI_CTRL, value);
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while (timeout--) {
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ctrl = dwmci_readl(host, DWMCI_CTRL);
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if (!(ctrl & DWMCI_RESET_ALL))
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return 1;
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}
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return 0;
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}
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static void dwmci_set_idma_desc(struct dwmci_idmac *idmac,
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u32 desc0, u32 desc1, u32 desc2)
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{
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struct dwmci_idmac *desc = idmac;
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desc->flags = desc0;
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desc->cnt = desc1;
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desc->addr = desc2;
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desc->next_addr = (unsigned int)desc + sizeof(struct dwmci_idmac);
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}
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static void dwmci_prepare_data(struct dwmci_host *host,
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struct mmc_data *data,
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struct dwmci_idmac *cur_idmac,
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void *bounce_buffer)
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{
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unsigned long ctrl;
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unsigned int i = 0, flags, cnt, blk_cnt;
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ulong data_start, data_end;
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blk_cnt = data->blocks;
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dwmci_wait_reset(host, DWMCI_CTRL_FIFO_RESET);
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data_start = (ulong)cur_idmac;
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dwmci_writel(host, DWMCI_DBADDR, (unsigned int)cur_idmac);
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do {
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flags = DWMCI_IDMAC_OWN | DWMCI_IDMAC_CH ;
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flags |= (i == 0) ? DWMCI_IDMAC_FS : 0;
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if (blk_cnt <= 8) {
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flags |= DWMCI_IDMAC_LD;
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cnt = data->blocksize * blk_cnt;
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} else
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cnt = data->blocksize * 8;
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dwmci_set_idma_desc(cur_idmac, flags, cnt,
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(u32)bounce_buffer + (i * PAGE_SIZE));
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if (blk_cnt <= 8)
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break;
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blk_cnt -= 8;
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cur_idmac++;
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i++;
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} while(1);
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data_end = (ulong)cur_idmac;
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flush_dcache_range(data_start, data_end + ARCH_DMA_MINALIGN);
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ctrl = dwmci_readl(host, DWMCI_CTRL);
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ctrl |= DWMCI_IDMAC_EN | DWMCI_DMA_EN;
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dwmci_writel(host, DWMCI_CTRL, ctrl);
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ctrl = dwmci_readl(host, DWMCI_BMOD);
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ctrl |= DWMCI_BMOD_IDMAC_FB | DWMCI_BMOD_IDMAC_EN;
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dwmci_writel(host, DWMCI_BMOD, ctrl);
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dwmci_writel(host, DWMCI_BLKSIZ, data->blocksize);
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dwmci_writel(host, DWMCI_BYTCNT, data->blocksize * data->blocks);
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}
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static int dwmci_set_transfer_mode(struct dwmci_host *host,
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struct mmc_data *data)
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{
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unsigned long mode;
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mode = DWMCI_CMD_DATA_EXP;
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if (data->flags & MMC_DATA_WRITE)
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mode |= DWMCI_CMD_RW;
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return mode;
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}
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static int dwmci_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
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struct mmc_data *data)
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{
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struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
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ALLOC_CACHE_ALIGN_BUFFER(struct dwmci_idmac, cur_idmac,
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data ? DIV_ROUND_UP(data->blocks, 8) : 0);
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int flags = 0, i;
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unsigned int timeout = 100000;
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u32 retry = 10000;
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u32 mask, ctrl;
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ulong start = get_timer(0);
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struct bounce_buffer bbstate;
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while (dwmci_readl(host, DWMCI_STATUS) & DWMCI_BUSY) {
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if (get_timer(start) > timeout) {
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printf("Timeout on data busy\n");
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return TIMEOUT;
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}
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}
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dwmci_writel(host, DWMCI_RINTSTS, DWMCI_INTMSK_ALL);
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if (data) {
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if (data->flags == MMC_DATA_READ) {
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bounce_buffer_start(&bbstate, (void*)data->dest,
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data->blocksize *
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data->blocks, GEN_BB_WRITE);
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} else {
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bounce_buffer_start(&bbstate, (void*)data->src,
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data->blocksize *
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data->blocks, GEN_BB_READ);
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}
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dwmci_prepare_data(host, data, cur_idmac,
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bbstate.bounce_buffer);
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}
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dwmci_writel(host, DWMCI_CMDARG, cmd->cmdarg);
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if (data)
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flags = dwmci_set_transfer_mode(host, data);
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if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
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return -1;
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if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
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flags |= DWMCI_CMD_ABORT_STOP;
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else
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flags |= DWMCI_CMD_PRV_DAT_WAIT;
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if (cmd->resp_type & MMC_RSP_PRESENT) {
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flags |= DWMCI_CMD_RESP_EXP;
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if (cmd->resp_type & MMC_RSP_136)
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flags |= DWMCI_CMD_RESP_LENGTH;
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}
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if (cmd->resp_type & MMC_RSP_CRC)
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flags |= DWMCI_CMD_CHECK_CRC;
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flags |= (cmd->cmdidx | DWMCI_CMD_START | DWMCI_CMD_USE_HOLD_REG);
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debug("Sending CMD%d\n",cmd->cmdidx);
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dwmci_writel(host, DWMCI_CMD, flags);
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for (i = 0; i < retry; i++) {
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mask = dwmci_readl(host, DWMCI_RINTSTS);
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if (mask & DWMCI_INTMSK_CDONE) {
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if (!data)
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dwmci_writel(host, DWMCI_RINTSTS, mask);
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break;
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}
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}
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if (i == retry)
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return TIMEOUT;
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if (mask & DWMCI_INTMSK_RTO) {
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debug("Response Timeout..\n");
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return TIMEOUT;
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} else if (mask & DWMCI_INTMSK_RE) {
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debug("Response Error..\n");
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return -1;
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}
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if (cmd->resp_type & MMC_RSP_PRESENT) {
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if (cmd->resp_type & MMC_RSP_136) {
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cmd->response[0] = dwmci_readl(host, DWMCI_RESP3);
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cmd->response[1] = dwmci_readl(host, DWMCI_RESP2);
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cmd->response[2] = dwmci_readl(host, DWMCI_RESP1);
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cmd->response[3] = dwmci_readl(host, DWMCI_RESP0);
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} else {
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cmd->response[0] = dwmci_readl(host, DWMCI_RESP0);
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}
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}
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if (data) {
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do {
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mask = dwmci_readl(host, DWMCI_RINTSTS);
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if (mask & (DWMCI_DATA_ERR | DWMCI_DATA_TOUT)) {
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debug("DATA ERROR!\n");
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return -1;
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}
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} while (!(mask & DWMCI_INTMSK_DTO));
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dwmci_writel(host, DWMCI_RINTSTS, mask);
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ctrl = dwmci_readl(host, DWMCI_CTRL);
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ctrl &= ~(DWMCI_DMA_EN);
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dwmci_writel(host, DWMCI_CTRL, ctrl);
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bounce_buffer_stop(&bbstate);
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}
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udelay(100);
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return 0;
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}
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static int dwmci_setup_bus(struct dwmci_host *host, u32 freq)
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{
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u32 div, status;
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int timeout = 10000;
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unsigned long sclk;
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if ((freq == host->clock) || (freq == 0))
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return 0;
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/*
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* If host->get_mmc_clk didn't define,
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* then assume that host->bus_hz is source clock value.
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* host->bus_hz should be set from user.
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*/
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if (host->get_mmc_clk)
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sclk = host->get_mmc_clk(host);
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else if (host->bus_hz)
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sclk = host->bus_hz;
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else {
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printf("Didn't get source clock value..\n");
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return -EINVAL;
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}
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div = DIV_ROUND_UP(sclk, 2 * freq);
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dwmci_writel(host, DWMCI_CLKENA, 0);
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dwmci_writel(host, DWMCI_CLKSRC, 0);
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dwmci_writel(host, DWMCI_CLKDIV, div);
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dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
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DWMCI_CMD_UPD_CLK | DWMCI_CMD_START);
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do {
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status = dwmci_readl(host, DWMCI_CMD);
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if (timeout-- < 0) {
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printf("TIMEOUT error!!\n");
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return -ETIMEDOUT;
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}
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} while (status & DWMCI_CMD_START);
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dwmci_writel(host, DWMCI_CLKENA, DWMCI_CLKEN_ENABLE |
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DWMCI_CLKEN_LOW_PWR);
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dwmci_writel(host, DWMCI_CMD, DWMCI_CMD_PRV_DAT_WAIT |
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DWMCI_CMD_UPD_CLK | DWMCI_CMD_START);
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timeout = 10000;
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do {
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status = dwmci_readl(host, DWMCI_CMD);
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if (timeout-- < 0) {
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printf("TIMEOUT error!!\n");
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return -ETIMEDOUT;
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}
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} while (status & DWMCI_CMD_START);
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host->clock = freq;
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return 0;
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}
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static void dwmci_set_ios(struct mmc *mmc)
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{
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struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
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u32 ctype;
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debug("Buswidth = %d, clock: %d\n",mmc->bus_width, mmc->clock);
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dwmci_setup_bus(host, mmc->clock);
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switch (mmc->bus_width) {
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case 8:
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ctype = DWMCI_CTYPE_8BIT;
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break;
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case 4:
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ctype = DWMCI_CTYPE_4BIT;
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break;
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default:
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ctype = DWMCI_CTYPE_1BIT;
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break;
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}
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dwmci_writel(host, DWMCI_CTYPE, ctype);
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if (host->clksel)
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host->clksel(host);
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}
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static int dwmci_init(struct mmc *mmc)
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{
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struct dwmci_host *host = (struct dwmci_host *)mmc->priv;
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if (host->board_init)
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host->board_init(host);
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dwmci_writel(host, DWMCI_PWREN, 1);
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if (!dwmci_wait_reset(host, DWMCI_RESET_ALL)) {
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debug("%s[%d] Fail-reset!!\n",__func__,__LINE__);
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return -1;
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}
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/* Enumerate at 400KHz */
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dwmci_setup_bus(host, mmc->f_min);
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dwmci_writel(host, DWMCI_RINTSTS, 0xFFFFFFFF);
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dwmci_writel(host, DWMCI_INTMASK, 0);
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dwmci_writel(host, DWMCI_TMOUT, 0xFFFFFFFF);
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dwmci_writel(host, DWMCI_IDINTEN, 0);
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dwmci_writel(host, DWMCI_BMOD, 1);
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if (host->fifoth_val) {
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dwmci_writel(host, DWMCI_FIFOTH, host->fifoth_val);
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}
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dwmci_writel(host, DWMCI_CLKENA, 0);
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dwmci_writel(host, DWMCI_CLKSRC, 0);
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return 0;
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}
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int add_dwmci(struct dwmci_host *host, u32 max_clk, u32 min_clk)
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{
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struct mmc *mmc;
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int err = 0;
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mmc = calloc(sizeof(struct mmc), 1);
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if (!mmc) {
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printf("mmc calloc fail!\n");
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return -1;
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}
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mmc->priv = host;
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host->mmc = mmc;
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sprintf(mmc->name, "%s", host->name);
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mmc->send_cmd = dwmci_send_cmd;
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mmc->set_ios = dwmci_set_ios;
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mmc->init = dwmci_init;
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mmc->f_min = min_clk;
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mmc->f_max = max_clk;
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mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
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mmc->host_caps = host->caps;
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if (host->buswidth == 8) {
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mmc->host_caps |= MMC_MODE_8BIT;
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mmc->host_caps &= ~MMC_MODE_4BIT;
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} else {
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mmc->host_caps |= MMC_MODE_4BIT;
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mmc->host_caps &= ~MMC_MODE_8BIT;
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}
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mmc->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_HC;
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err = mmc_register(mmc);
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return err;
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}
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