mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-27 04:18:51 +09:00
![Peng Fan](/assets/img/avatar_default.png)
lpuart0 is the uart used by SPL and U-Boot proper, and DM_SERIAL is enabled. Since uclass power domain is also enabled, to make lpuart work properly, need add u-boot,dm-spl for lpuart power domain and its parent. Signed-off-by: Peng Fan <peng.fan@nxp.com>
126 lines
1.0 KiB
Plaintext
126 lines
1.0 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2018 NXP
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*/
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&{/imx8qx-pm} {
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u-boot,dm-spl;
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};
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&mu {
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u-boot,dm-spl;
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};
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&clk {
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u-boot,dm-spl;
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};
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&iomuxc {
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u-boot,dm-spl;
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};
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&pd_lsio {
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u-boot,dm-spl;
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};
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&pd_lsio_gpio0 {
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u-boot,dm-spl;
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};
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&pd_lsio_gpio1 {
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u-boot,dm-spl;
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};
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&pd_lsio_gpio2 {
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u-boot,dm-spl;
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};
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&pd_lsio_gpio3 {
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u-boot,dm-spl;
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};
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&pd_lsio_gpio4 {
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u-boot,dm-spl;
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};
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&pd_lsio_gpio5 {
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u-boot,dm-spl;
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};
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&pd_lsio_gpio6 {
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u-boot,dm-spl;
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};
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&pd_lsio_gpio7 {
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u-boot,dm-spl;
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};
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&pd_conn {
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u-boot,dm-spl;
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};
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&pd_conn_sdch0 {
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u-boot,dm-spl;
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};
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&pd_conn_sdch1 {
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u-boot,dm-spl;
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};
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&pd_conn_sdch2 {
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u-boot,dm-spl;
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};
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&pd_dma {
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u-boot,dm-spl;
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};
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&pd_dma_lpuart0 {
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u-boot,dm-spl;
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};
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&gpio0 {
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u-boot,dm-spl;
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};
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&gpio1 {
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u-boot,dm-spl;
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};
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&gpio2 {
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u-boot,dm-spl;
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};
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&gpio3 {
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u-boot,dm-spl;
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};
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&gpio4 {
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u-boot,dm-spl;
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};
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&gpio5 {
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u-boot,dm-spl;
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};
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&gpio6 {
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u-boot,dm-spl;
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};
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&gpio7 {
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u-boot,dm-spl;
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};
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&lpuart0 {
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u-boot,dm-spl;
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};
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&usdhc1 {
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u-boot,dm-spl;
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};
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&usdhc2 {
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u-boot,dm-spl;
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};
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