Chris Zhong b5788dc0dd rockchip: rk3288: correct sdram setting ... The DMC driver in v3.14 kernel[0] get the ddr setting from PMU_SYS_REG2, and it expects uboot to store the value using a same protocol. But now the ddr setting value is different with DMC, so if you enable the DMC, system would crash in kernel. Correct the sdram setting here, according to the requirements of kernel. [0] https://chromium.googlesource.com/chromiumos/third_party/kernel/+/ chromeos-3.14/drivers/clk/rockchip/clk-rk3288-dmc.c Signed-off-by: Chris Zhong <zyw@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org>		2016-03-10 08:32:01 -07:00
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rk3036	rockchip: rk3036: change ddr frequency to 400M	2016-03-10 08:32:01 -07:00
rk3288	rockchip: rk3288: correct sdram setting	2016-03-10 08:32:01 -07:00
board.c	rockchip: Add a simple 'clock' command	2016-01-21 20:42:36 -07:00
Kconfig	Revert "rockchip: Add max spl size & spl header configs"	2015-12-13 17:07:06 -07:00
Makefile	rockchip: clk: Make rkclk_get_clk() SoC-specific	2016-01-21 20:42:35 -07:00
rk_timer.c	rockchip: add timer driver	2015-12-01 08:07:22 -07:00
rk3036-board-spl.c	rockchip: Use the debug UART on rk3036	2016-01-12 10:19:09 -07:00
rk3288-board-spl.c	rockchip: make configure_emmc() empty for Firefly-RK3288	2016-03-10 08:32:01 -07:00