mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-21 01:18:52 +09:00
557 lines
12 KiB
C
557 lines
12 KiB
C
/*
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* (C) Copyright 2002
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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/*
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* UART test
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*
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* The Serial Management Controllers (SMC) and the Serial Communication
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* Controllers (SCC) listed in ctlr_list array below are tested in
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* the loopback UART mode.
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* The controllers are configured accordingly and several characters
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* are transmitted. The configurable test parameters are:
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* MIN_PACKET_LENGTH - minimum size of packet to transmit
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* MAX_PACKET_LENGTH - maximum size of packet to transmit
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* TEST_NUM - number of tests
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*/
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#include <post.h>
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#if CONFIG_POST & CONFIG_SYS_POST_UART
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#if defined(CONFIG_8xx)
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#include <commproc.h>
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#elif defined(CONFIG_MPC8260)
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#include <asm/cpm_8260.h>
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#else
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#error "Apparently a bad configuration, please fix."
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#endif
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#include <command.h>
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#include <serial.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define CTLR_SMC 0
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#define CTLR_SCC 1
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/* The list of controllers to test */
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#if defined(CONFIG_MPC823)
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static int ctlr_list[][2] =
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{ {CTLR_SMC, 0}, {CTLR_SMC, 1}, {CTLR_SCC, 1} };
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#else
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static int ctlr_list[][2] = { };
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#endif
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#define CTRL_LIST_SIZE (sizeof(ctlr_list) / sizeof(ctlr_list[0]))
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static struct {
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void (*init) (int index);
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void (*halt) (int index);
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void (*putc) (int index, const char c);
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int (*getc) (int index);
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} ctlr_proc[2];
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static char *ctlr_name[2] = { "SMC", "SCC" };
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static int proff_smc[] = { PROFF_SMC1, PROFF_SMC2 };
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static int proff_scc[] =
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{ PROFF_SCC1, PROFF_SCC2, PROFF_SCC3, PROFF_SCC4 };
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/*
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* SMC callbacks
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*/
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static void smc_init (int smc_index)
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{
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static int cpm_cr_ch[] = { CPM_CR_CH_SMC1, CPM_CR_CH_SMC2 };
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volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
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volatile smc_t *sp;
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volatile smc_uart_t *up;
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volatile cbd_t *tbdf, *rbdf;
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volatile cpm8xx_t *cp = &(im->im_cpm);
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uint dpaddr;
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/* initialize pointers to SMC */
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sp = (smc_t *) & (cp->cp_smc[smc_index]);
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up = (smc_uart_t *) & cp->cp_dparam[proff_smc[smc_index]];
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/* Disable transmitter/receiver.
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*/
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sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
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/* Enable SDMA.
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*/
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im->im_siu_conf.sc_sdcr = 1;
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/* clear error conditions */
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#ifdef CONFIG_SYS_SDSR
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im->im_sdma.sdma_sdsr = CONFIG_SYS_SDSR;
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#else
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im->im_sdma.sdma_sdsr = 0x83;
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#endif
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/* clear SDMA interrupt mask */
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#ifdef CONFIG_SYS_SDMR
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im->im_sdma.sdma_sdmr = CONFIG_SYS_SDMR;
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#else
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im->im_sdma.sdma_sdmr = 0x00;
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#endif
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#if defined(CONFIG_FADS)
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/* Enable RS232 */
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*((uint *) BCSR1) &=
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~(smc_index == 1 ? BCSR1_RS232EN_1 : BCSR1_RS232EN_2);
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#endif
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#if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC)
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/* Enable Monitor Port Transceiver */
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*((uchar *) BCSR0) |= BCSR0_ENMONXCVR;
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#endif
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/* Set the physical address of the host memory buffers in
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* the buffer descriptors.
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*/
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#ifdef CONFIG_SYS_ALLOC_DPRAM
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dpaddr = dpram_alloc_align (sizeof (cbd_t) * 2 + 2, 8);
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#else
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dpaddr = CPM_POST_BASE;
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#endif
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/* Allocate space for two buffer descriptors in the DP ram.
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* For now, this address seems OK, but it may have to
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* change with newer versions of the firmware.
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* damm: allocating space after the two buffers for rx/tx data
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*/
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rbdf = (cbd_t *) & cp->cp_dpmem[dpaddr];
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rbdf->cbd_bufaddr = (uint) (rbdf + 2);
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rbdf->cbd_sc = 0;
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tbdf = rbdf + 1;
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tbdf->cbd_bufaddr = ((uint) (rbdf + 2)) + 1;
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tbdf->cbd_sc = 0;
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/* Set up the uart parameters in the parameter ram.
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*/
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up->smc_rbase = dpaddr;
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up->smc_tbase = dpaddr + sizeof (cbd_t);
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up->smc_rfcr = SMC_EB;
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up->smc_tfcr = SMC_EB;
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#if defined(CONFIG_MBX)
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board_serial_init ();
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#endif
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/* Set UART mode, 8 bit, no parity, one stop.
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* Enable receive and transmit.
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* Set local loopback mode.
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*/
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sp->smc_smcmr = smcr_mk_clen (9) | SMCMR_SM_UART | (ushort) 0x0004;
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/* Mask all interrupts and remove anything pending.
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*/
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sp->smc_smcm = 0;
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sp->smc_smce = 0xff;
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/* Set up the baud rate generator.
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*/
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cp->cp_simode = 0x00000000;
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cp->cp_brgc1 =
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(((gd->cpu_clk / 16 / gd->baudrate) -
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1) << 1) | CPM_BRG_EN;
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/* Make the first buffer the only buffer.
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*/
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tbdf->cbd_sc |= BD_SC_WRAP;
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rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
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/* Single character receive.
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*/
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up->smc_mrblr = 1;
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up->smc_maxidl = 0;
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/* Initialize Tx/Rx parameters.
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*/
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while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
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;
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cp->cp_cpcr =
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mk_cr_cmd (cpm_cr_ch[smc_index], CPM_CR_INIT_TRX) | CPM_CR_FLG;
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while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
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;
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/* Enable transmitter/receiver.
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*/
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sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN;
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}
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static void smc_halt(int smc_index)
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{
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}
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static void smc_putc (int smc_index, const char c)
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{
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volatile cbd_t *tbdf;
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volatile char *buf;
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volatile smc_uart_t *up;
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volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
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volatile cpm8xx_t *cpmp = &(im->im_cpm);
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up = (smc_uart_t *) & cpmp->cp_dparam[proff_smc[smc_index]];
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tbdf = (cbd_t *) & cpmp->cp_dpmem[up->smc_tbase];
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/* Wait for last character to go.
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*/
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buf = (char *) tbdf->cbd_bufaddr;
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#if 0
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__asm__ ("eieio");
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while (tbdf->cbd_sc & BD_SC_READY)
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__asm__ ("eieio");
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#endif
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*buf = c;
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tbdf->cbd_datlen = 1;
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tbdf->cbd_sc |= BD_SC_READY;
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__asm__ ("eieio");
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#if 1
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while (tbdf->cbd_sc & BD_SC_READY)
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__asm__ ("eieio");
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#endif
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}
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static int smc_getc (int smc_index)
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{
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volatile cbd_t *rbdf;
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volatile unsigned char *buf;
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volatile smc_uart_t *up;
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volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
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volatile cpm8xx_t *cpmp = &(im->im_cpm);
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unsigned char c;
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int i;
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up = (smc_uart_t *) & cpmp->cp_dparam[proff_smc[smc_index]];
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rbdf = (cbd_t *) & cpmp->cp_dpmem[up->smc_rbase];
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/* Wait for character to show up.
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*/
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buf = (unsigned char *) rbdf->cbd_bufaddr;
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#if 0
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while (rbdf->cbd_sc & BD_SC_EMPTY);
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#else
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for (i = 100; i > 0; i--) {
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if (!(rbdf->cbd_sc & BD_SC_EMPTY))
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break;
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udelay (1000);
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}
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if (i == 0)
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return -1;
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#endif
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c = *buf;
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rbdf->cbd_sc |= BD_SC_EMPTY;
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return (c);
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}
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/*
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* SCC callbacks
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*/
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static void scc_init (int scc_index)
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{
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static int cpm_cr_ch[] = {
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CPM_CR_CH_SCC1,
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CPM_CR_CH_SCC2,
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CPM_CR_CH_SCC3,
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CPM_CR_CH_SCC4,
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};
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volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
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volatile scc_t *sp;
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volatile scc_uart_t *up;
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volatile cbd_t *tbdf, *rbdf;
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volatile cpm8xx_t *cp = &(im->im_cpm);
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uint dpaddr;
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/* initialize pointers to SCC */
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sp = (scc_t *) & (cp->cp_scc[scc_index]);
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up = (scc_uart_t *) & cp->cp_dparam[proff_scc[scc_index]];
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/* Disable transmitter/receiver.
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*/
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sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
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/* Allocate space for two buffer descriptors in the DP ram.
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*/
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#ifdef CONFIG_SYS_ALLOC_DPRAM
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dpaddr = dpram_alloc_align (sizeof (cbd_t) * 2 + 2, 8);
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#else
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dpaddr = CPM_POST_BASE;
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#endif
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/* Enable SDMA.
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*/
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im->im_siu_conf.sc_sdcr = 0x0001;
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/* Set the physical address of the host memory buffers in
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* the buffer descriptors.
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*/
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rbdf = (cbd_t *) & cp->cp_dpmem[dpaddr];
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rbdf->cbd_bufaddr = (uint) (rbdf + 2);
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rbdf->cbd_sc = 0;
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tbdf = rbdf + 1;
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tbdf->cbd_bufaddr = ((uint) (rbdf + 2)) + 1;
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tbdf->cbd_sc = 0;
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/* Set up the baud rate generator.
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*/
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cp->cp_sicr &= ~(0x000000FF << (8 * scc_index));
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/* no |= needed, since BRG1 is 000 */
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cp->cp_brgc1 =
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(((gd->cpu_clk / 16 / gd->baudrate) -
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1) << 1) | CPM_BRG_EN;
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/* Set up the uart parameters in the parameter ram.
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*/
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up->scc_genscc.scc_rbase = dpaddr;
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up->scc_genscc.scc_tbase = dpaddr + sizeof (cbd_t);
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/* Initialize Tx/Rx parameters.
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*/
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while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
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;
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cp->cp_cpcr =
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mk_cr_cmd (cpm_cr_ch[scc_index], CPM_CR_INIT_TRX) | CPM_CR_FLG;
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while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */
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;
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up->scc_genscc.scc_rfcr = SCC_EB | 0x05;
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up->scc_genscc.scc_tfcr = SCC_EB | 0x05;
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up->scc_genscc.scc_mrblr = 1; /* Single character receive */
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up->scc_maxidl = 0; /* disable max idle */
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up->scc_brkcr = 1; /* send one break character on stop TX */
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up->scc_parec = 0;
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up->scc_frmec = 0;
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up->scc_nosec = 0;
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up->scc_brkec = 0;
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up->scc_uaddr1 = 0;
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up->scc_uaddr2 = 0;
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up->scc_toseq = 0;
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up->scc_char1 = 0x8000;
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up->scc_char2 = 0x8000;
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up->scc_char3 = 0x8000;
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up->scc_char4 = 0x8000;
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up->scc_char5 = 0x8000;
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up->scc_char6 = 0x8000;
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up->scc_char7 = 0x8000;
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up->scc_char8 = 0x8000;
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up->scc_rccm = 0xc0ff;
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/* Set low latency / small fifo.
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*/
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sp->scc_gsmrh = SCC_GSMRH_RFW;
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/* Set UART mode
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*/
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sp->scc_gsmrl &= ~0xF;
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sp->scc_gsmrl |= SCC_GSMRL_MODE_UART;
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/* Set local loopback mode.
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*/
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sp->scc_gsmrl &= ~SCC_GSMRL_DIAG_LE;
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sp->scc_gsmrl |= SCC_GSMRL_DIAG_LOOP;
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/* Set clock divider 16 on Tx and Rx
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*/
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sp->scc_gsmrl |= (SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16);
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sp->scc_psmr |= SCU_PSMR_CL;
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/* Mask all interrupts and remove anything pending.
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*/
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sp->scc_sccm = 0;
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sp->scc_scce = 0xffff;
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sp->scc_dsr = 0x7e7e;
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sp->scc_psmr = 0x3000;
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/* Make the first buffer the only buffer.
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*/
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tbdf->cbd_sc |= BD_SC_WRAP;
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rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP;
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/* Enable transmitter/receiver.
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*/
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sp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
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}
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static void scc_halt(int scc_index)
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{
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volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
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volatile cpm8xx_t *cp = &(im->im_cpm);
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volatile scc_t *sp = (scc_t *) & (cp->cp_scc[scc_index]);
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sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT | SCC_GSMRL_DIAG_LE);
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}
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static void scc_putc (int scc_index, const char c)
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{
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volatile cbd_t *tbdf;
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volatile char *buf;
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volatile scc_uart_t *up;
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volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
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volatile cpm8xx_t *cpmp = &(im->im_cpm);
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up = (scc_uart_t *) & cpmp->cp_dparam[proff_scc[scc_index]];
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tbdf = (cbd_t *) & cpmp->cp_dpmem[up->scc_genscc.scc_tbase];
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/* Wait for last character to go.
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*/
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buf = (char *) tbdf->cbd_bufaddr;
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#if 0
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__asm__ ("eieio");
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while (tbdf->cbd_sc & BD_SC_READY)
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__asm__ ("eieio");
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#endif
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*buf = c;
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tbdf->cbd_datlen = 1;
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tbdf->cbd_sc |= BD_SC_READY;
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__asm__ ("eieio");
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#if 1
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while (tbdf->cbd_sc & BD_SC_READY)
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__asm__ ("eieio");
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#endif
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}
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static int scc_getc (int scc_index)
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{
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volatile cbd_t *rbdf;
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volatile unsigned char *buf;
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volatile scc_uart_t *up;
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volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
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volatile cpm8xx_t *cpmp = &(im->im_cpm);
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unsigned char c;
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int i;
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up = (scc_uart_t *) & cpmp->cp_dparam[proff_scc[scc_index]];
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rbdf = (cbd_t *) & cpmp->cp_dpmem[up->scc_genscc.scc_rbase];
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/* Wait for character to show up.
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*/
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buf = (unsigned char *) rbdf->cbd_bufaddr;
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#if 0
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while (rbdf->cbd_sc & BD_SC_EMPTY);
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#else
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for (i = 100; i > 0; i--) {
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if (!(rbdf->cbd_sc & BD_SC_EMPTY))
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break;
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udelay (1000);
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}
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if (i == 0)
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return -1;
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#endif
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c = *buf;
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rbdf->cbd_sc |= BD_SC_EMPTY;
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return (c);
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}
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/*
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* Test routines
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*/
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static int test_ctlr (int ctlr, int index)
|
|
{
|
|
int res = -1;
|
|
char test_str[] = "*** UART Test String ***\r\n";
|
|
int i;
|
|
|
|
ctlr_proc[ctlr].init (index);
|
|
|
|
for (i = 0; i < sizeof (test_str) - 1; i++) {
|
|
ctlr_proc[ctlr].putc (index, test_str[i]);
|
|
if (ctlr_proc[ctlr].getc (index) != test_str[i])
|
|
goto Done;
|
|
}
|
|
|
|
res = 0;
|
|
|
|
Done:
|
|
ctlr_proc[ctlr].halt (index);
|
|
|
|
if (res != 0) {
|
|
post_log ("uart %s%d test failed\n",
|
|
ctlr_name[ctlr], index + 1);
|
|
}
|
|
|
|
return res;
|
|
}
|
|
|
|
int uart_post_test (int flags)
|
|
{
|
|
int res = 0;
|
|
int i;
|
|
|
|
ctlr_proc[CTLR_SMC].init = smc_init;
|
|
ctlr_proc[CTLR_SMC].halt = smc_halt;
|
|
ctlr_proc[CTLR_SMC].putc = smc_putc;
|
|
ctlr_proc[CTLR_SMC].getc = smc_getc;
|
|
|
|
ctlr_proc[CTLR_SCC].init = scc_init;
|
|
ctlr_proc[CTLR_SCC].halt = scc_halt;
|
|
ctlr_proc[CTLR_SCC].putc = scc_putc;
|
|
ctlr_proc[CTLR_SCC].getc = scc_getc;
|
|
|
|
for (i = 0; i < CTRL_LIST_SIZE; i++) {
|
|
if (test_ctlr (ctlr_list[i][0], ctlr_list[i][1]) != 0) {
|
|
res = -1;
|
|
}
|
|
}
|
|
|
|
#if !defined(CONFIG_8xx_CONS_NONE)
|
|
serial_reinit_all ();
|
|
#endif
|
|
|
|
return res;
|
|
}
|
|
|
|
#endif /* CONFIG_POST & CONFIG_SYS_POST_UART */
|