Jagan Teki 5cbc866981 ram: rk3399: Don't wait for PLL lock in lpddr4 ... lpddr4 has PLL bypass mode during phy initialization phase, which does all pll configurations. So no need to wait explicitly during pctl config. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>		2019-07-20 23:59:44 +08:00
..
dmc-rk3368.c	rockchip: dmc: rk3368: update rank number for evb-px5	2019-05-08 17:34:12 +08:00
Kconfig	ram: rockchip: Kconfig: Add RK3399 LPDDR4 entry	2019-07-20 23:59:44 +08:00
Makefile	ram: rockchip: Add debug sdram driver	2019-07-19 11:11:09 +08:00
sdram_debug.c	ram: rk3399: debug: Add sdram_print_stride	2019-07-19 11:11:10 +08:00
sdram_rk322x.c	Revert "rockchip: rk322x: ram: enable DRAM init in SPL instead of TPL"	2019-05-08 17:34:12 +08:00
sdram_rk3128.c	rockchip: use 'arch-rockchip' as header file path	2019-05-01 00:00:05 +02:00
sdram_rk3188.c	rockchip: use 'arch-rockchip' as header file path	2019-05-01 00:00:05 +02:00
sdram_rk3288.c	rockchip: use 'arch-rockchip' as header file path	2019-05-01 00:00:05 +02:00
sdram_rk3328.c	rockchip: use 'arch-rockchip' as header file path	2019-05-01 00:00:05 +02:00
sdram_rk3399.c	ram: rk3399: Don't wait for PLL lock in lpddr4	2019-07-20 23:59:44 +08:00