mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-08 04:06:15 +09:00
609 lines
20 KiB
C
609 lines
20 KiB
C
/*
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* (C) Copyright 2005-2007
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* Samsung Electronics.
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* Kyungmin Park <kyungmin.park@samsung.com>
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*
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* Derived from omap2420
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/arch/omap2420.h>
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#include <asm/io.h>
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#include <asm/arch/bits.h>
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#include <asm/arch/mux.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/sys_info.h>
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#include <asm/arch/mem.h>
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#include <i2c.h>
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#include <asm/mach-types.h>
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void wait_for_command_complete(unsigned int wd_base);
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/*******************************************************
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* Routine: delay
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* Description: spinning delay to use before udelay works
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******************************************************/
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static inline void delay(unsigned long loops) {
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__asm__ volatile ("1:\n" "subs %0, %1, #1\n"
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"bne 1b":"=r" (loops):"0"(loops)); }
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/*****************************************
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* Routine: board_init
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* Description: Early hardware init.
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*****************************************/
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int board_init(void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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gpmc_init(); /* in SRAM or SDRM, finish GPMC */
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gd->bd->bi_arch_number = 919;
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/* adress of boot parameters */
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gd->bd->bi_boot_params = (OMAP2420_SDRC_CS0 + 0x100);
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return 0;
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}
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/**********************************************************
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* Routine: s_init
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* Description: Does early system init of muxing and clocks.
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* - Called path is with sram stack.
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**********************************************************/
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void s_init(void)
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{
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watchdog_init();
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set_muxconf_regs();
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delay(100);
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peripheral_enable();
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icache_enable();
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}
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/*******************************************************
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* Routine: misc_init_r
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* Description: Init ethernet (done here so udelay works)
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********************************************************/
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int misc_init_r(void)
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{
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ether_init(); /* better done here so timers are init'ed */
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return (0);
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}
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/****************************************
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* Routine: watchdog_init
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* Description: Shut down watch dogs
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*****************************************/
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void watchdog_init(void)
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{
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/* There are 4 watch dogs. 1 secure, and 3 general purpose.
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* The ROM takes care of the secure one. Of the 3 GP ones,
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* 1 can reset us directly, the other 2 only generate MPU interrupts.
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*/
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__raw_writel(WD_UNLOCK1, WD2_BASE + WSPR);
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wait_for_command_complete(WD2_BASE);
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__raw_writel(WD_UNLOCK2, WD2_BASE + WSPR);
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#define MPU_WD_CLOCKED 1
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#if MPU_WD_CLOCKED /* value 0x10 stick on aptix, BIT4 polarity seems oppsite */
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__raw_writel(WD_UNLOCK1, WD3_BASE + WSPR);
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wait_for_command_complete(WD3_BASE);
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__raw_writel(WD_UNLOCK2, WD3_BASE + WSPR);
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__raw_writel(WD_UNLOCK1, WD4_BASE + WSPR);
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wait_for_command_complete(WD4_BASE);
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__raw_writel(WD_UNLOCK2, WD4_BASE + WSPR);
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#endif
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}
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/******************************************************
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* Routine: wait_for_command_complete
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* Description: Wait for posting to finish on watchdog
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******************************************************/
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void wait_for_command_complete(unsigned int wd_base) {
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int pending = 1;
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do {
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pending = __raw_readl(wd_base + WWPS);
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} while (pending);
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}
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/*******************************************************************
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* Routine:ether_init
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* Description: take the Ethernet controller out of reset and wait
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* for the EEPROM load to complete.
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******************************************************************/
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void ether_init(void)
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{
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#ifdef CONFIG_DRIVER_LAN91C96
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int cnt = 20;
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__raw_writeb(0x03, OMAP2420_CTRL_BASE + 0x0f2); /*protect->gpio74 */
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__raw_writew(0x0, LAN_RESET_REGISTER);
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do {
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__raw_writew(0x1, LAN_RESET_REGISTER);
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udelay(100);
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if (cnt == 0) {
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printf("1. eth reset err\n");
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goto eth_reset_err_out;
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}
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--cnt;
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} while (__raw_readw(LAN_RESET_REGISTER) != 0x1);
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cnt = 20;
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do {
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__raw_writew(0x0, LAN_RESET_REGISTER);
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udelay(100);
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if (cnt == 0) {
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printf("2. eth reset err\n");
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goto eth_reset_err_out;
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}
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--cnt;
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} while (__raw_readw(LAN_RESET_REGISTER) != 0x0000);
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udelay(1000);
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*((volatile unsigned char *)ETH_CONTROL_REG) &= ~0x01;
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udelay(1000);
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eth_reset_err_out:
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return;
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#endif
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}
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/**********************************************
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* Routine: dram_init
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* Description: sets uboots idea of sdram size
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**********************************************/
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int dram_init(void)
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{
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DECLARE_GLOBAL_DATA_PTR;
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unsigned int size0 = 0, size1 = 0;
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u32 mtype, btype, rev = 0, cpu = 0;
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#define NOT_EARLY 0
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btype = get_board_type();
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mtype = get_mem_type();
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rev = get_cpu_rev();
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cpu = get_cpu_type();
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display_board_info(btype);
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if ((mtype == DDR_COMBO) || (mtype == DDR_STACKED)) {
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printf("ddr combo\n");
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do_sdrc_init(SDRC_CS1_OSET, NOT_EARLY); /* init other chip select */
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}
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size0 = get_sdr_cs_size(SDRC_CS0_OSET);
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size1 = get_sdr_cs_size(SDRC_CS1_OSET);
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = size0;
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#if CONFIG_NR_DRAM_BANKS > 1
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gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + size0;
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gd->bd->bi_dram[1].size = size1;
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#endif
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return 0;
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}
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/**********************************************************
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* Routine: set_muxconf_regs
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* Description: Setting up the configuration Mux registers
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* specific to the hardware
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*********************************************************/
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void set_muxconf_regs(void)
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{
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muxSetupSDRC();
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muxSetupGPMC();
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muxSetupUsb0(); /* USB Device */
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muxSetupUsbHost(); /* USB Host */
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muxSetupUART1();
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muxSetupLCD();
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muxSetupMMCSD();
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muxSetupTouchScreen();
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}
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/*****************************************************************
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* Routine: peripheral_enable
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* Description: Enable the clks & power for perifs (GPT2, UART1,...)
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******************************************************************/
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void peripheral_enable(void)
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{
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unsigned int v, if_clks = 0, func_clks = 0;
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/* Enable GP2 timer. */
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if_clks |= BIT4 | BIT3;
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func_clks |= BIT4 | BIT3;
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v = __raw_readl(CM_CLKSEL2_CORE) | 0x4 | 0x2; /* Sys_clk input OMAP2420_GPT2 */
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__raw_writel(v, CM_CLKSEL2_CORE);
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__raw_writel(0x1, CM_CLKSEL_WKUP);
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#ifdef CFG_NS16550
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/* Enable UART1 clock */
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func_clks |= BIT21;
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if_clks |= BIT21;
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#endif
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v = __raw_readl(CM_ICLKEN1_CORE) | if_clks; /* Interface clocks on */
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__raw_writel(v, CM_ICLKEN1_CORE);
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v = __raw_readl(CM_FCLKEN1_CORE) | func_clks; /* Functional Clocks on */
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__raw_writel(v, CM_FCLKEN1_CORE);
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delay(1000);
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#ifndef KERNEL_UPDATED
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{
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#define V1 0xffffffff
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#define V2 0x00000007
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__raw_writel(V1, CM_FCLKEN1_CORE);
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__raw_writel(V2, CM_FCLKEN2_CORE);
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__raw_writel(V1, CM_ICLKEN1_CORE);
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__raw_writel(V1, CM_ICLKEN2_CORE);
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}
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#endif
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}
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/****************************************
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* Routine: muxSetupUsb0 (ostboot)
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* Description: Setup usb muxing
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*****************************************/
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void muxSetupUsb0(void)
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{
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volatile uint8 *MuxConfigReg;
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MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_PUEN;
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*MuxConfigReg &= (uint8) (~0x1F);
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MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_VP;
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*MuxConfigReg &= (uint8) (~0x1F);
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MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_VM;
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*MuxConfigReg &= (uint8) (~0x1F);
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MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_RCV;
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*MuxConfigReg &= (uint8) (~0x1F);
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MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_TXEN;
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*MuxConfigReg &= (uint8) (~0x1F);
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MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_SE0;
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*MuxConfigReg &= (uint8) (~0x1F);
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MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB0_DAT;
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*MuxConfigReg &= (uint8) (~0x1F);
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}
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#define CONTROL_PADCONF_USB1_RCV ((volatile uint8 *)0x480000EB)
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#define CONTROL_PADCONF_USB1_TXEN ((volatile uint8 *)0x480000EC)
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#define CONTROL_PADCONF_GPIO69 ((volatile uint8 *)0x480000ED)
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#define CONTROL_PADCONF_GPIO70 ((volatile uint8 *)0x480000EE)
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#define CONTROL_PADCONF_GPIO102 ((volatile uint8 *)0x48000116)
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#define CONTROL_PADCONF_GPIO103 ((volatile uint8 *)0x48000117)
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#define CONTROL_PADCONF_GPIO104 ((volatile uint8 *)0x48000118)
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#define CONTROL_PADCONF_GPIO105 ((volatile uint8 *)0x48000119)
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/****************************************
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* Routine: muxSetupUSBHost (ostboot)
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* Description: Setup USB Host muxing
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*****************************************/
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void muxSetupUsbHost(void)
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{
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volatile uint8 *MuxConfigReg;
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/* V19 */
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MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB1_RCV;
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*MuxConfigReg = 1;
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/* W20 */
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MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_USB1_TXEN;
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*MuxConfigReg = 1;
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/* N14 */
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MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPIO69;
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*MuxConfigReg = 3;
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/* P15 */
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MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPIO70;
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*MuxConfigReg = 3;
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/* L18 */
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MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPIO102;
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*MuxConfigReg = 3;
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/* L19 */
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MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPIO103;
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*MuxConfigReg = 3;
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/* K15 */
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MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPIO104;
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*MuxConfigReg = 3;
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/* K14 */
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MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPIO105;
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*MuxConfigReg = 3;
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}
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/****************************************
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* Routine: muxSetupUART1 (ostboot)
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* Description: Set up uart1 muxing
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*****************************************/
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void muxSetupUART1(void)
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{
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volatile unsigned char *MuxConfigReg;
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/* UART1_CTS pin configuration, PIN = D21 */
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MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_CTS;
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*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
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/* UART1_RTS pin configuration, PIN = H21 */
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MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_RTS;
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*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
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/* UART1_TX pin configuration, PIN = L20 */
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MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_TX;
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*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
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/* UART1_RX pin configuration, PIN = T21 */
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MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_UART1_RX;
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*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
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}
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/****************************************
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* Routine: muxSetupLCD (ostboot)
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* Description: Setup lcd muxing
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*****************************************/
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void muxSetupLCD(void)
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{
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volatile unsigned char *MuxConfigReg;
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/* LCD_D0 pin configuration, PIN = Y7 */
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MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D0;
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*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
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/* LCD_D1 pin configuration, PIN = P10 */
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MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D1;
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*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
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/* LCD_D2 pin configuration, PIN = V8 */
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MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D2;
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*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
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/* LCD_D3 pin configuration, PIN = Y8 */
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MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D3;
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*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
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/* LCD_D4 pin configuration, PIN = W8 */
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MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D4;
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*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
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/* LCD_D5 pin configuration, PIN = R10 */
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MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D5;
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*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
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/* LCD_D6 pin configuration, PIN = Y9 */
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MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D6;
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*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
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/* LCD_D7 pin configuration, PIN = V9 */
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MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D7;
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*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
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/* LCD_D8 pin configuration, PIN = W9 */
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MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D8;
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*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
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/* LCD_D9 pin configuration, PIN = P11 */
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MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D9;
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*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
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/* LCD_D10 pin configuration, PIN = V10 */
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MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D10;
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*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
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/* LCD_D11 pin configuration, PIN = Y10 */
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MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D11;
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*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
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/* LCD_D12 pin configuration, PIN = W10 */
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MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D12;
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*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
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/* LCD_D13 pin configuration, PIN = R11 */
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MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D13;
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*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
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/* LCD_D14 pin configuration, PIN = V11 */
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MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D14;
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*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
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/* LCD_D15 pin configuration, PIN = W11 */
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MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D15;
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*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
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/* LCD_D16 pin configuration, PIN = P12 */
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MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D16;
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*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
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/* LCD_D17 pin configuration, PIN = R12 */
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MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D17;
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*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
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/* LCD_PCLK pin configuration, PIN = W6 */
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MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_PCLK;
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*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
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/* LCD_VSYNC pin configuration, PIN = V7 */
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MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_VSYNC;
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*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
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/* LCD_HSYNC pin configuration, PIN = Y6 */
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MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_HSYNC;
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*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
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/* LCD_ACBIAS pin configuration, PIN = W7 */
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MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_ACBIAS;
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*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
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}
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/****************************************
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* Routine: muxSetupMMCSD (ostboot)
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* Description: set up MMC muxing
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*****************************************/
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void muxSetupMMCSD(void)
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{
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volatile unsigned char *MuxConfigReg;
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/* SDMMC_CLKI pin configuration, PIN = H15 */
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MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CLKI;
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*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
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/* SDMMC_CLKO pin configuration, PIN = G19 */
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MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CLKO;
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*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
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|
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/* SDMMC_CMD pin configuration, PIN = H18 */
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MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CMD;
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*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
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/* External pull-ups are present. */
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/* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
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|
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/* SDMMC_DAT0 pin configuration, PIN = F20 */
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MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT0;
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*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
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/* External pull-ups are present. */
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/* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
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|
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/* SDMMC_DAT1 pin configuration, PIN = H14 */
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MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT1;
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*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
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/* External pull-ups are present. */
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/* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
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|
|
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/* SDMMC_DAT2 pin configuration, PIN = E19 */
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MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT2;
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*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
|
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/* External pull-ups are present. */
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/* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
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|
|
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/* SDMMC_DAT3 pin configuration, PIN = D19 */
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MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT3;
|
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*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
|
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/* External pull-ups are present. */
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|
/* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
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|
|
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/* SDMMC_DDIR0 pin configuration, PIN = F19 */
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MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR0;
|
|
*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
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|
|
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/* SDMMC_DDIR1 pin configuration, PIN = E20 */
|
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MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR1;
|
|
*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
|
|
|
|
/* SDMMC_DDIR2 pin configuration, PIN = F18 */
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR2;
|
|
*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
|
|
|
|
/* SDMMC_DDIR3 pin configuration, PIN = E18 */
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR3;
|
|
*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
|
|
|
|
/* SDMMC_CDIR pin configuration, PIN = G18 */
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CMD_DIR;
|
|
*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
|
|
}
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|
|
|
/******************************************
|
|
* Routine: muxSetupTouchScreen (ostboot)
|
|
* Description: Set up touch screen muxing
|
|
*******************************************/
|
|
void muxSetupTouchScreen(void)
|
|
{
|
|
volatile unsigned char *MuxConfigReg;
|
|
|
|
/* SPI1_CLK pin configuration, PIN = U18 */
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_CLK;
|
|
*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
|
|
|
|
/* SPI1_MOSI pin configuration, PIN = V20 */
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_SIMO;
|
|
*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
|
|
|
|
/* SPI1_MISO pin configuration, PIN = T18 */
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_SOMI;
|
|
*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
|
|
|
|
/* SPI1_nCS0 pin configuration, PIN = U19 */
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_NCS0;
|
|
*MuxConfigReg = 0x00; /* Mode = 0, PUPD=Disabled */
|
|
|
|
#define CONTROL_PADCONF_GPIO85 CONTROL_PADCONF_SPI1_NCS1
|
|
|
|
/* PEN_IRQ pin configuration, PIN = N15 */
|
|
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_GPIO85;
|
|
*MuxConfigReg = 0x03; /* Mode = 3, PUPD=Disabled */
|
|
}
|
|
|
|
/***************************************************************
|
|
* Routine: muxSetupGPMC (ostboot)
|
|
* Description: Configures balls which cam up in protected mode
|
|
***************************************************************/
|
|
void muxSetupGPMC(void)
|
|
{
|
|
volatile uint8 *MuxConfigReg;
|
|
volatile unsigned int *MCR = (volatile unsigned int *)0x4800008C;
|
|
|
|
/* gpmc_io_dir */
|
|
*MCR = 0x19000000;
|
|
|
|
/* NOR FLASH CS0 */
|
|
/* signal - Gpmc_clk;
|
|
pin - J4; offset - 0x0088; mode - 0; Byte-3 Pull/up - N/A */
|
|
MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_D2_BYTE3;
|
|
*MuxConfigReg = 0x00;
|
|
|
|
/* MPDB(Multi Port Debug Port) CS1 */
|
|
/* signal - gpmc_ncs1;
|
|
pin - N8; offset - 0x008C; mode - 0; Byte-1 Pull/up - N/A */
|
|
MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE1;
|
|
*MuxConfigReg = 0x00;
|
|
|
|
/* signal - Gpmc_ncs2;
|
|
pin - E2; offset - 0x008C; mode - 0; Byte-2 Pull/up - N/A */
|
|
MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE2;
|
|
*MuxConfigReg = 0x00;
|
|
|
|
/* signal - Gpmc_ncs3;
|
|
pin - N2; offset - 0x008C; mode - 0; Byte-3 Pull/up - N/A */
|
|
MuxConfigReg = (volatile uint8 *)CONTROL_PADCONF_GPMC_NCS0_BYTE3;
|
|
*MuxConfigReg = 0x00;
|
|
|
|
MuxConfigReg = (volatile uint8 *)((volatile unsigned char *)0x48000090);
|
|
*MuxConfigReg = 0x00;
|
|
MuxConfigReg = (volatile uint8 *)((volatile unsigned char *)0x48000091);
|
|
*MuxConfigReg = 0x00;
|
|
MuxConfigReg = (volatile uint8 *)((volatile unsigned char *)0x48000092);
|
|
*MuxConfigReg = 0x00;
|
|
MuxConfigReg = (volatile uint8 *)((volatile unsigned char *)0x48000093);
|
|
*MuxConfigReg = 0x00;
|
|
}
|
|
|
|
/****************************************************************
|
|
* Routine: muxSetupSDRC (ostboot)
|
|
* Description: Configures balls which come up in protected mode
|
|
****************************************************************/
|
|
void muxSetupSDRC(void)
|
|
{
|
|
/* It's set by IPL */
|
|
}
|