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https://github.com/brain-hackers/u-boot-brain
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![Tom Rini](/assets/img/avatar_default.png)
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
243 lines
5.9 KiB
C
243 lines
5.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
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*/
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#include <bouncebuf.h>
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#include <common.h>
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#include <malloc.h>
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#include <nand.h>
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#include <asm/io.h>
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#include "axs10x.h"
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DECLARE_GLOBAL_DATA_PTR;
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#define BUS_WIDTH 8 /* AXI data bus width in bytes */
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/* DMA buffer descriptor bits & masks */
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#define BD_STAT_OWN (1 << 31)
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#define BD_STAT_BD_FIRST (1 << 3)
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#define BD_STAT_BD_LAST (1 << 2)
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#define BD_SIZES_BUFFER1_MASK 0xfff
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#define BD_STAT_BD_COMPLETE (BD_STAT_BD_FIRST | BD_STAT_BD_LAST)
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/* Controller command flags */
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#define B_WFR (1 << 19) /* 1b - Wait for ready */
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#define B_LC (1 << 18) /* 1b - Last cycle */
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#define B_IWC (1 << 13) /* 1b - Interrupt when complete */
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/* NAND cycle types */
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#define B_CT_ADDRESS (0x0 << 16) /* Address operation */
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#define B_CT_COMMAND (0x1 << 16) /* Command operation */
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#define B_CT_WRITE (0x2 << 16) /* Write operation */
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#define B_CT_READ (0x3 << 16) /* Write operation */
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enum nand_isr_t {
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NAND_ISR_DATAREQUIRED = 0,
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NAND_ISR_TXUNDERFLOW,
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NAND_ISR_TXOVERFLOW,
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NAND_ISR_DATAAVAILABLE,
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NAND_ISR_RXUNDERFLOW,
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NAND_ISR_RXOVERFLOW,
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NAND_ISR_TXDMACOMPLETE,
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NAND_ISR_RXDMACOMPLETE,
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NAND_ISR_DESCRIPTORUNAVAILABLE,
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NAND_ISR_CMDDONE,
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NAND_ISR_CMDAVAILABLE,
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NAND_ISR_CMDERROR,
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NAND_ISR_DATATRANSFEROVER,
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NAND_ISR_NONE
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};
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enum nand_regs_t {
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AC_FIFO = 0, /* address and command fifo */
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IDMAC_BDADDR = 0x18, /* idmac descriptor list base address */
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INT_STATUS = 0x118, /* interrupt status register */
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INT_CLR_STATUS = 0x120, /* interrupt clear status register */
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};
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struct nand_bd {
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uint32_t status; /* DES0 */
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uint32_t sizes; /* DES1 */
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uint32_t buffer_ptr0; /* DES2 */
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uint32_t buffer_ptr1; /* DES3 */
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};
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#define NAND_REG_WRITE(r, v) \
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writel(v, (volatile void __iomem *)(CONFIG_SYS_NAND_BASE + r))
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#define NAND_REG_READ(r) \
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readl((const volatile void __iomem *)(CONFIG_SYS_NAND_BASE + r))
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static struct nand_bd *bd; /* DMA buffer descriptors */
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/**
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* axs101_nand_write_buf - write buffer to chip
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* @mtd: MTD device structure
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* @buf: data buffer
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* @len: number of bytes to write
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*/
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static uint32_t nand_flag_is_set(uint32_t flag)
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{
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uint32_t reg = NAND_REG_READ(INT_STATUS);
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if (reg & (1 << NAND_ISR_CMDERROR))
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return 0;
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if (reg & (1 << flag)) {
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NAND_REG_WRITE(INT_CLR_STATUS, 1 << flag);
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return 1;
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}
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return 0;
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}
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/**
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* axs101_nand_write_buf - write buffer to chip
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* @mtd: MTD device structure
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* @buf: data buffer
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* @len: number of bytes to write
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*/
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static void axs101_nand_write_buf(struct mtd_info *mtd, const u_char *buf,
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int len)
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{
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struct bounce_buffer bbstate;
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bounce_buffer_start(&bbstate, (void *)buf, len, GEN_BB_READ);
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/* Setup buffer descriptor */
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writel(BD_STAT_OWN | BD_STAT_BD_COMPLETE, &bd->status);
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writel(ALIGN(len, BUS_WIDTH) & BD_SIZES_BUFFER1_MASK, &bd->sizes);
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writel(bbstate.bounce_buffer, &bd->buffer_ptr0);
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writel(0, &bd->buffer_ptr1);
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/* Flush modified buffer descriptor */
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flush_dcache_range((unsigned long)bd,
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(unsigned long)bd + sizeof(struct nand_bd));
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/* Issue "write" command */
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NAND_REG_WRITE(AC_FIFO, B_CT_WRITE | B_WFR | B_IWC | B_LC | (len-1));
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/* Wait for NAND command and DMA to complete */
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while (!nand_flag_is_set(NAND_ISR_CMDDONE))
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;
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while (!nand_flag_is_set(NAND_ISR_TXDMACOMPLETE))
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;
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bounce_buffer_stop(&bbstate);
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}
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/**
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* axs101_nand_read_buf - read chip data into buffer
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* @mtd: MTD device structure
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* @buf: buffer to store data
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* @len: number of bytes to read
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*/
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static void axs101_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
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{
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struct bounce_buffer bbstate;
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bounce_buffer_start(&bbstate, buf, len, GEN_BB_WRITE);
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/* Setup buffer descriptor */
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writel(BD_STAT_OWN | BD_STAT_BD_COMPLETE, &bd->status);
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writel(ALIGN(len, BUS_WIDTH) & BD_SIZES_BUFFER1_MASK, &bd->sizes);
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writel(bbstate.bounce_buffer, &bd->buffer_ptr0);
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writel(0, &bd->buffer_ptr1);
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/* Flush modified buffer descriptor */
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flush_dcache_range((unsigned long)bd,
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(unsigned long)bd + sizeof(struct nand_bd));
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/* Issue "read" command */
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NAND_REG_WRITE(AC_FIFO, B_CT_READ | B_WFR | B_IWC | B_LC | (len - 1));
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/* Wait for NAND command and DMA to complete */
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while (!nand_flag_is_set(NAND_ISR_CMDDONE))
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;
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while (!nand_flag_is_set(NAND_ISR_RXDMACOMPLETE))
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;
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bounce_buffer_stop(&bbstate);
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}
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/**
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* axs101_nand_read_byte - read one byte from the chip
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* @mtd: MTD device structure
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*/
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static u_char axs101_nand_read_byte(struct mtd_info *mtd)
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{
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u8 byte;
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axs101_nand_read_buf(mtd, (uchar *)&byte, sizeof(byte));
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return byte;
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}
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/**
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* axs101_nand_read_word - read one word from the chip
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* @mtd: MTD device structure
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*/
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static u16 axs101_nand_read_word(struct mtd_info *mtd)
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{
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u16 word;
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axs101_nand_read_buf(mtd, (uchar *)&word, sizeof(word));
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return word;
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}
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/**
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* axs101_nand_hwcontrol - NAND control functions wrapper.
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* @mtd: MTD device structure
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* @cmd: Command
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*/
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static void axs101_nand_hwcontrol(struct mtd_info *mtdinfo, int cmd,
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unsigned int ctrl)
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{
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if (cmd == NAND_CMD_NONE)
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return;
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cmd = cmd & 0xff;
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switch (ctrl & (NAND_ALE | NAND_CLE)) {
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/* Address */
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case NAND_ALE:
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cmd |= B_CT_ADDRESS;
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break;
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/* Command */
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case NAND_CLE:
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cmd |= B_CT_COMMAND | B_WFR;
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break;
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default:
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debug("%s: unknown ctrl %#x\n", __func__, ctrl);
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}
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NAND_REG_WRITE(AC_FIFO, cmd | B_LC);
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while (!nand_flag_is_set(NAND_ISR_CMDDONE))
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;
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}
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int board_nand_init(struct nand_chip *nand)
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{
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bd = (struct nand_bd *)memalign(ARCH_DMA_MINALIGN,
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sizeof(struct nand_bd));
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/* Set buffer descriptor address in IDMAC */
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NAND_REG_WRITE(IDMAC_BDADDR, bd);
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nand->ecc.mode = NAND_ECC_SOFT;
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nand->cmd_ctrl = axs101_nand_hwcontrol;
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nand->read_byte = axs101_nand_read_byte;
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nand->read_word = axs101_nand_read_word;
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nand->write_buf = axs101_nand_write_buf;
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nand->read_buf = axs101_nand_read_buf;
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/* MBv3 has NAND IC with 16-bit data bus */
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if (gd->board_type == AXS_MB_V3)
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nand->options |= NAND_BUSWIDTH_16;
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return 0;
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}
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