mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-22 09:58:52 +09:00
![Tom Rini](/assets/img/avatar_default.png)
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
421 lines
9.7 KiB
C
421 lines
9.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2011 Renesas Solutions Corp.
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*/
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#include <common.h>
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#include <environment.h>
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#include <malloc.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <asm/mmc.h>
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#include <spi.h>
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#include <spi_flash.h>
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int checkboard(void)
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{
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puts("BOARD: R0P7757LC0030RL board\n");
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return 0;
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}
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static void init_gctrl(void)
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{
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struct gctrl_regs *gctrl = GCTRL_BASE;
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unsigned long graofst;
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graofst = (SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET) >> 24;
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writel(graofst | 0x20000f00, &gctrl->gracr3);
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}
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static int init_pcie_bridge_from_spi(void *buf, size_t size)
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{
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struct spi_flash *spi;
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int ret;
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unsigned long pcie_addr;
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spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
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if (!spi) {
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printf("%s: spi_flash probe error.\n", __func__);
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return 1;
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}
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if (is_sh7757_b0())
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pcie_addr = SH7757LCR_PCIEBRG_ADDR_B0;
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else
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pcie_addr = SH7757LCR_PCIEBRG_ADDR;
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ret = spi_flash_read(spi, pcie_addr, size, buf);
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if (ret) {
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printf("%s: spi_flash read error.\n", __func__);
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spi_flash_free(spi);
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return 1;
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}
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spi_flash_free(spi);
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return 0;
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}
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static void init_pcie_bridge(void)
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{
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struct pciebrg_regs *pciebrg = PCIEBRG_BASE;
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struct pcie_setup_regs *pcie_setup = PCIE_SETUP_BASE;
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int i;
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unsigned char *data;
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unsigned short tmp;
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unsigned long pcie_size;
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if (!(readw(&pciebrg->ctrl_h8s) & 0x0001))
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return;
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if (is_sh7757_b0())
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pcie_size = SH7757LCR_PCIEBRG_SIZE_B0;
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else
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pcie_size = SH7757LCR_PCIEBRG_SIZE;
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data = malloc(pcie_size);
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if (!data) {
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printf("%s: malloc error.\n", __func__);
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return;
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}
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if (init_pcie_bridge_from_spi(data, pcie_size)) {
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free(data);
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return;
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}
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if (data[0] == 0xff && data[1] == 0xff && data[2] == 0xff &&
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data[3] == 0xff) {
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free(data);
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printf("%s: skipped initialization\n", __func__);
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return;
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}
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writew(0xa501, &pciebrg->ctrl_h8s); /* reset */
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writew(0x0000, &pciebrg->cp_ctrl);
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writew(0x0000, &pciebrg->cp_addr);
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for (i = 0; i < pcie_size; i += 2) {
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tmp = (data[i] << 8) | data[i + 1];
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writew(tmp, &pciebrg->cp_data);
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}
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writew(0xa500, &pciebrg->ctrl_h8s); /* start */
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if (!is_sh7757_b0())
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writel(0x00000001, &pcie_setup->pbictl3);
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free(data);
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}
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static void init_usb_phy(void)
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{
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struct usb_common_regs *common0 = USB0_COMMON_BASE;
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struct usb_common_regs *common1 = USB1_COMMON_BASE;
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struct usb0_phy_regs *phy = USB0_PHY_BASE;
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struct usb1_port_regs *port = USB1_PORT_BASE;
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struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE;
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writew(0x0100, &phy->reset); /* set reset */
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/* port0 = USB0, port1 = USB1 */
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writew(0x0002, &phy->portsel);
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writel(0x0001, &port->port1sel); /* port1 = Host */
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writew(0x0111, &phy->reset); /* clear reset */
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writew(0x4000, &common0->suspmode);
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writew(0x4000, &common1->suspmode);
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#if defined(__LITTLE_ENDIAN)
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writel(0x00000000, &align->ehcidatac);
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writel(0x00000000, &align->ohcidatac);
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#endif
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}
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static void set_mac_to_sh_eth_register(int channel, char *mac_string)
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{
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struct ether_mac_regs *ether;
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unsigned char mac[6];
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unsigned long val;
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eth_parse_enetaddr(mac_string, mac);
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if (!channel)
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ether = ETHER0_MAC_BASE;
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else
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ether = ETHER1_MAC_BASE;
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val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
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writel(val, ðer->mahr);
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val = (mac[4] << 8) | mac[5];
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writel(val, ðer->malr);
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}
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static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string)
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{
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struct ether_mac_regs *ether;
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unsigned char mac[6];
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unsigned long val;
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eth_parse_enetaddr(mac_string, mac);
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if (!channel)
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ether = GETHER0_MAC_BASE;
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else
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ether = GETHER1_MAC_BASE;
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val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
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writel(val, ðer->mahr);
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val = (mac[4] << 8) | mac[5];
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writel(val, ðer->malr);
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}
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/*****************************************************************
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* This PMB must be set on this timing. The lowlevel_init is run on
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* Area 0(phys 0x00000000), so we have to map it.
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*
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* The new PMB table is following:
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* ent virt phys v sz c wt
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* 0 0xa0000000 0x40000000 1 128M 0 1
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* 1 0xa8000000 0x48000000 1 128M 0 1
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* 2 0xb0000000 0x50000000 1 128M 0 1
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* 3 0xb8000000 0x58000000 1 128M 0 1
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* 4 0x80000000 0x40000000 1 128M 1 1
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* 5 0x88000000 0x48000000 1 128M 1 1
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* 6 0x90000000 0x50000000 1 128M 1 1
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* 7 0x98000000 0x58000000 1 128M 1 1
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*/
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static void set_pmb_on_board_init(void)
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{
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struct mmu_regs *mmu = MMU_BASE;
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/* clear ITLB */
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writel(0x00000004, &mmu->mmucr);
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/* delete PMB for SPIBOOT */
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writel(0, PMB_ADDR_BASE(0));
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writel(0, PMB_DATA_BASE(0));
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/* add PMB for SDRAM(0x40000000 - 0x47ffffff) */
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/* ppn ub v s1 s0 c wt */
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writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0));
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writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0));
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writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2));
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writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2));
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writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3));
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writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3));
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writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4));
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writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4));
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writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6));
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writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6));
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writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7));
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writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7));
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}
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int board_init(void)
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{
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struct gether_control_regs *gether = GETHER_CONTROL_BASE;
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set_pmb_on_board_init();
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/* enable RMII's MDIO (disable GRMII's MDIO) */
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writel(0x00030000, &gether->gbecont);
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init_gctrl();
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init_usb_phy();
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return 0;
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}
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int board_mmc_init(bd_t *bis)
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{
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return mmcif_mmc_init();
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}
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static int get_sh_eth_mac_raw(unsigned char *buf, int size)
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{
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struct spi_flash *spi;
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int ret;
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spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
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if (spi == NULL) {
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printf("%s: spi_flash probe error.\n", __func__);
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return 1;
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}
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ret = spi_flash_read(spi, SH7757LCR_ETHERNET_MAC_BASE, size, buf);
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if (ret) {
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printf("%s: spi_flash read error.\n", __func__);
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spi_flash_free(spi);
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return 1;
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}
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spi_flash_free(spi);
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return 0;
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}
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static int get_sh_eth_mac(int channel, char *mac_string, unsigned char *buf)
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{
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memcpy(mac_string, &buf[channel * (SH7757LCR_ETHERNET_MAC_SIZE + 1)],
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SH7757LCR_ETHERNET_MAC_SIZE);
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mac_string[SH7757LCR_ETHERNET_MAC_SIZE] = 0x00; /* terminate */
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return 0;
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}
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static void init_ethernet_mac(void)
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{
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char mac_string[64];
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char env_string[64];
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int i;
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unsigned char *buf;
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buf = malloc(256);
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if (!buf) {
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printf("%s: malloc error.\n", __func__);
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return;
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}
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get_sh_eth_mac_raw(buf, 256);
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/* Fast Ethernet */
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for (i = 0; i < SH7757LCR_ETHERNET_NUM_CH; i++) {
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get_sh_eth_mac(i, mac_string, buf);
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if (i == 0)
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env_set("ethaddr", mac_string);
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else {
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sprintf(env_string, "eth%daddr", i);
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env_set(env_string, mac_string);
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}
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set_mac_to_sh_eth_register(i, mac_string);
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}
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/* Gigabit Ethernet */
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for (i = 0; i < SH7757LCR_GIGA_ETHERNET_NUM_CH; i++) {
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get_sh_eth_mac(i + SH7757LCR_ETHERNET_NUM_CH, mac_string, buf);
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sprintf(env_string, "eth%daddr", i + SH7757LCR_ETHERNET_NUM_CH);
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env_set(env_string, mac_string);
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set_mac_to_sh_giga_eth_register(i, mac_string);
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}
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free(buf);
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}
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static void init_pcie(void)
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{
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struct pcie_setup_regs *pcie_setup = PCIE_SETUP_BASE;
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struct pcie_system_bus_regs *pcie_sysbus = PCIE_SYSTEM_BUS_BASE;
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writel(0x00000ff2, &pcie_setup->ladmsk0);
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writel(0x00000001, &pcie_setup->barmap);
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writel(0xffcaa000, &pcie_setup->lad0);
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writel(0x00030000, &pcie_sysbus->endictl0);
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writel(0x00000003, &pcie_sysbus->endictl1);
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writel(0x00000004, &pcie_setup->pbictl2);
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}
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static void finish_spiboot(void)
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{
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struct gctrl_regs *gctrl = GCTRL_BASE;
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/*
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* SH7757 B0 does not use LBSC.
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* So if we set SPIBOOTCAN to 1, SH7757 can not access Area0.
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* This setting is not cleared by manual reset, So we have to set it
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* to 0.
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*/
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writel(0x00000000, &gctrl->spibootcan);
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}
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int board_late_init(void)
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{
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init_ethernet_mac();
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init_pcie_bridge();
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init_pcie();
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finish_spiboot();
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return 0;
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}
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int do_sh_g200(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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struct gctrl_regs *gctrl = GCTRL_BASE;
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unsigned long graofst;
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writel(0xfedcba98, &gctrl->wprotect);
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graofst = (SH7757LCR_SDRAM_PHYS_TOP + SH7757LCR_GRA_OFFSET) >> 24;
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writel(graofst | 0xa0000f00, &gctrl->gracr3);
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return 0;
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}
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U_BOOT_CMD(
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sh_g200, 1, 1, do_sh_g200,
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"enable sh-g200",
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"enable SH-G200 bus (disable PCIe-G200)"
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);
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int do_write_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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int i, ret;
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char mac_string[256];
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struct spi_flash *spi;
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unsigned char *buf;
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if (argc != 5) {
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buf = malloc(256);
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if (!buf) {
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printf("%s: malloc error.\n", __func__);
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return 1;
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}
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get_sh_eth_mac_raw(buf, 256);
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/* print current MAC address */
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for (i = 0; i < 4; i++) {
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get_sh_eth_mac(i, mac_string, buf);
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if (i < 2)
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printf(" ETHERC ch%d = %s\n", i, mac_string);
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else
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printf("GETHERC ch%d = %s\n", i-2, mac_string);
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}
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free(buf);
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return 0;
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}
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/* new setting */
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memset(mac_string, 0xff, sizeof(mac_string));
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sprintf(mac_string, "%s\t%s\t%s\t%s",
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argv[1], argv[2], argv[3], argv[4]);
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/* write MAC data to SPI rom */
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spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
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if (!spi) {
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printf("%s: spi_flash probe error.\n", __func__);
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return 1;
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}
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ret = spi_flash_erase(spi, SH7757LCR_ETHERNET_MAC_BASE_SPI,
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SH7757LCR_SPI_SECTOR_SIZE);
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if (ret) {
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printf("%s: spi_flash erase error.\n", __func__);
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return 1;
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}
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ret = spi_flash_write(spi, SH7757LCR_ETHERNET_MAC_BASE_SPI,
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sizeof(mac_string), mac_string);
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if (ret) {
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printf("%s: spi_flash write error.\n", __func__);
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spi_flash_free(spi);
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return 1;
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}
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spi_flash_free(spi);
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puts("The writing of the MAC address to SPI ROM was completed.\n");
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return 0;
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}
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U_BOOT_CMD(
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write_mac, 5, 1, do_write_mac,
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"write MAC address for ETHERC/GETHERC",
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"[ETHERC ch0] [ETHERC ch1] [GETHERC ch0] [GETHERC ch1]\n"
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);
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