mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-19 01:27:59 +09:00
e85497a930
Up to now the RAM size of the sandbox is hard coded as 128 MiB. This does not allow testing the correct handling of addresses outside the 32bit range. 128 MiB is also rather small when tracing functions where the trace is written to RAM. Provide configuration variable CONFIG_SANDBOX_RAM_SIZE_MB to set the RAM size in MiB. It defaults to 128 MiB with a minimum of 64 MiB. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
139 lines
3.2 KiB
C
139 lines
3.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (c) 2011 The Chromium OS Authors.
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#ifdef FTRACE
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#define CONFIG_TRACE
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#define CONFIG_TRACE_BUFFER_SIZE (16 << 20)
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#define CONFIG_TRACE_EARLY_SIZE (16 << 20)
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#define CONFIG_TRACE_EARLY
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#define CONFIG_TRACE_EARLY_ADDR 0x00100000
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#endif
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#ifndef CONFIG_SPL_BUILD
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#define CONFIG_IO_TRACE
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#endif
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#ifndef CONFIG_TIMER
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#define CONFIG_SYS_TIMER_RATE 1000000
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#endif
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#define CONFIG_LMB
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#define CONFIG_HOST_MAX_DEVICES 4
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/*
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* Size of malloc() pool, before and after relocation
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*/
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#define CONFIG_MALLOC_F_ADDR 0x0010000
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#define CONFIG_SYS_MALLOC_LEN (32 << 20) /* 32MB */
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#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
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/* turn on command-line edit/c/auto */
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/* SPI - enable all SPI flash types for testing purposes */
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#define CONFIG_I2C_EDID
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/* Memory things - we don't really want a memory test */
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#define CONFIG_SYS_LOAD_ADDR 0x00000000
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#define CONFIG_SYS_FDT_LOAD_ADDR 0x100
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#define CONFIG_PHYSMEM
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/* Size of our emulated memory */
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#define SB_CONCAT(x, y) x ## y
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#define SB_TO_UL(s) SB_CONCAT(s, UL)
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#define CONFIG_SYS_SDRAM_BASE 0
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#define CONFIG_SYS_SDRAM_SIZE \
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(SB_TO_UL(CONFIG_SANDBOX_RAM_SIZE_MB) << 20)
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#define CONFIG_SYS_MONITOR_BASE 0
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#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
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115200}
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#define BOOT_TARGET_DEVICES(func) \
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func(HOST, host, 1) \
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func(HOST, host, 0)
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#ifdef __ASSEMBLY__
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#define BOOTENV
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#else
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#include <config_distro_bootcmd.h>
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#endif
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#define CONFIG_KEEP_SERVERADDR
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#define CONFIG_UDP_CHECKSUM
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#define CONFIG_TIMESTAMP
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#define CONFIG_BOOTP_SEND_HOSTNAME
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#define CONFIG_BOOTP_SERVERIP
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#ifndef SANDBOX_NO_SDL
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#define CONFIG_SANDBOX_SDL
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#endif
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/* LCD and keyboard require SDL support */
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#ifdef CONFIG_SANDBOX_SDL
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#define LCD_BPP LCD_COLOR16
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#define CONFIG_LCD_BMP_RLE8
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#define CONFIG_VIDEO_BMP_RLE8
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#define CONFIG_SPLASH_SCREEN_ALIGN
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#define CONFIG_KEYBOARD
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#define SANDBOX_SERIAL_SETTINGS "stdin=serial,cros-ec-keyb,usbkbd\0" \
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"stdout=serial,vidconsole\0" \
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"stderr=serial,vidconsole\0"
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#else
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#define SANDBOX_SERIAL_SETTINGS "stdin=serial\0" \
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"stdout=serial,vidconsole\0" \
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"stderr=serial,vidconsole\0"
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#endif
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#define SANDBOX_ETH_SETTINGS "ethaddr=00:00:11:22:33:44\0" \
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"eth3addr=00:00:11:22:33:45\0" \
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"eth5addr=00:00:11:22:33:46\0" \
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"eth6addr=00:00:11:22:33:47\0" \
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"ipaddr=1.2.3.4\0"
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#define MEM_LAYOUT_ENV_SETTINGS \
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"bootm_size=0x10000000\0" \
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"kernel_addr_r=0x1000000\0" \
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"fdt_addr_r=0xc00000\0" \
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"ramdisk_addr_r=0x2000000\0" \
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"scriptaddr=0x1000\0" \
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"pxefile_addr_r=0x2000\0"
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#define CONFIG_EXTRA_ENV_SETTINGS \
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SANDBOX_SERIAL_SETTINGS \
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SANDBOX_ETH_SETTINGS \
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BOOTENV \
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MEM_LAYOUT_ENV_SETTINGS
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#ifndef CONFIG_SPL_BUILD
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#define CONFIG_SYS_IDE_MAXBUS 1
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#define CONFIG_SYS_ATA_IDE0_OFFSET 0
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#define CONFIG_SYS_IDE_MAXDEVICE 2
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#define CONFIG_SYS_ATA_BASE_ADDR 0x100
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#define CONFIG_SYS_ATA_DATA_OFFSET 0
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#define CONFIG_SYS_ATA_REG_OFFSET 1
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#define CONFIG_SYS_ATA_ALT_OFFSET 2
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#define CONFIG_SYS_ATA_STRIDE 4
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#endif
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#define CONFIG_SCSI_AHCI_PLAT
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#define CONFIG_SYS_SCSI_MAX_DEVICE 2
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#define CONFIG_SYS_SCSI_MAX_SCSI_ID 8
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#define CONFIG_SYS_SCSI_MAX_LUN 4
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#define CONFIG_SYS_SATA_MAX_DEVICE 2
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#define CONFIG_MISC_INIT_F
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#endif
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