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https://github.com/brain-hackers/u-boot-brain
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fbe44dd1aa
T1023 and T1024 have 4 SerDes lanes. Fix macro SRDS_MAX_LANES and use this macro instead of hard-coded value in t1024_serdes.c. Signed-off-by: Paulo Zaneti <paulo.zaneti@datacom.ind.br> Signed-off-by: York Sun <york.sun@nxp.com>
55 lines
1.6 KiB
C
55 lines
1.6 KiB
C
/*
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* Copyright 2014 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/fsl_serdes.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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static u8 serdes_cfg_tbl[][SRDS_MAX_LANES] = {
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[0x40] = {PCIE1, PCIE1, PCIE1, PCIE1},
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[0xD5] = {QSGMII_FM1_A, PCIE3, PCIE2, PCIE1},
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[0xD6] = {QSGMII_FM1_A, PCIE3, PCIE2, SATA1},
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[0x95] = {XFI_FM1_MAC1, PCIE3, PCIE2, PCIE1},
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[0x99] = {XFI_FM1_MAC1, PCIE3, SGMII_FM1_DTSEC2, PCIE1},
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[0x46] = {PCIE1, PCIE1, PCIE2, SATA1},
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[0x47] = {PCIE1, PCIE1, PCIE2, SGMII_FM1_DTSEC1},
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[0x56] = {PCIE1, PCIE3, PCIE2, SATA1},
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[0x5A] = {PCIE1, PCIE3, SGMII_FM1_DTSEC2, SATA1},
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[0x5B] = {PCIE1, PCIE3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC1},
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[0x5F] = {PCIE1, PCIE3, SGMII_2500_FM1_DTSEC2, SGMII_2500_FM1_DTSEC1},
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[0x6A] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC2, SATA1},
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[0x6B] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_FM1_DTSEC2, SGMII_FM1_DTSEC1},
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[0x6F] = {PCIE1, SGMII_FM1_DTSEC3, SGMII_2500_FM1_DTSEC2,
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SGMII_2500_FM1_DTSEC1},
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[0x77] = {PCIE1, SGMII_2500_FM1_DTSEC3, PCIE2, SGMII_FM1_DTSEC1},
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[0x7F] = {PCIE1, SGMII_2500_FM1_DTSEC3, SGMII_2500_FM1_DTSEC2,
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SGMII_2500_FM1_DTSEC1},
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[0x119] = {AURORA, PCIE3, SGMII_FM1_DTSEC2, PCIE1},
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[0x135] = {AURORA, SGMII_2500_FM1_DTSEC3, PCIE2, PCIE1},
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};
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enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
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{
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return serdes_cfg_tbl[cfg][lane];
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}
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int is_serdes_prtcl_valid(int serdes, u32 prtcl)
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{
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int i;
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if (prtcl >= ARRAY_SIZE(serdes_cfg_tbl))
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return 0;
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for (i = 0; i < SRDS_MAX_LANES; i++) {
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if (serdes_cfg_tbl[prtcl][i] != NONE)
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return 1;
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}
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return 0;
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}
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