mirror of
https://github.com/brain-hackers/u-boot-brain
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379 lines
8.6 KiB
C
379 lines
8.6 KiB
C
/*
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* (C) Copyright 2002
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* Rich Ireland, Enterasys Networks, rireland@enterasys.com.
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* Keith Outwater, keith_outwater@mvis.com.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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/*
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* Virtex2 FPGA configuration support for the GEN860T computer
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*/
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#include <common.h>
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#include <virtex2.h>
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#include <command.h>
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#include "fpga.h"
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DECLARE_GLOBAL_DATA_PTR;
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#if defined(CONFIG_FPGA)
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#if 0
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#define GEN860T_FPGA_DEBUG
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#endif
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#ifdef GEN860T_FPGA_DEBUG
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#define PRINTF(fmt,args...) printf (fmt ,##args)
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#else
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#define PRINTF(fmt,args...)
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#endif
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/*
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* Port bit numbers for the Selectmap controls
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*/
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#define FPGA_INIT_BIT_NUM 22 /* PB22 */
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#define FPGA_RESET_BIT_NUM 11 /* PC11 */
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#define FPGA_DONE_BIT_NUM 16 /* PB16 */
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#define FPGA_PROGRAM_BIT_NUM 7 /* PA7 */
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/* Note that these are pointers to code that is in Flash. They will be
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* relocated at runtime.
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*/
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Xilinx_Virtex2_Slave_SelectMap_fns fpga_fns = {
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fpga_pre_config_fn,
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fpga_pgm_fn,
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fpga_init_fn,
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fpga_err_fn,
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fpga_done_fn,
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fpga_clk_fn,
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fpga_cs_fn,
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fpga_wr_fn,
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fpga_read_data_fn,
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fpga_write_data_fn,
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fpga_busy_fn,
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fpga_abort_fn,
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fpga_post_config_fn
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};
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Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
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{Xilinx_Virtex2,
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slave_selectmap,
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XILINX_XC2V3000_SIZE,
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(void *) &fpga_fns,
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0}
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};
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/*
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* Display FPGA revision information
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*/
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void print_fpga_revision (void)
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{
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vu_long *rev_p = (vu_long *) 0x60000008;
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printf ("FPGA Revision 0x%.8lx"
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" (Date %.2lx/%.2lx/%.2lx, Status \"%.1lx\", Version %.3lu)\n",
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*rev_p,
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((*rev_p >> 28) & 0xf),
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((*rev_p >> 20) & 0xff),
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((*rev_p >> 12) & 0xff),
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((*rev_p >> 8) & 0xf), (*rev_p & 0xff));
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}
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/*
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* Perform a simple test of the FPGA to processor interface using the FPGA's
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* inverting bus test register. The great thing about doing a read/write
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* test on a register that inverts it's contents is that you avoid any
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* problems with bus charging.
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* Return 0 on failure, 1 on success.
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*/
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int test_fpga_ibtr (void)
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{
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vu_long *ibtr_p = (vu_long *) 0x60000010;
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vu_long readback;
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vu_long compare;
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int i;
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int j;
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int k;
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int pass = 1;
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static const ulong bitpattern[] = {
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0xdeadbeef, /* magic ID pattern for debug */
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0x00000001, /* single bit */
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0x00000003, /* two adjacent bits */
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0x00000007, /* three adjacent bits */
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0x0000000F, /* four adjacent bits */
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0x00000005, /* two non-adjacent bits */
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0x00000015, /* three non-adjacent bits */
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0x00000055, /* four non-adjacent bits */
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0xaaaaaaaa, /* alternating 1/0 */
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};
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for (i = 0; i < 1024; i++) {
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for (j = 0; j < 31; j++) {
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for (k = 0;
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k < sizeof (bitpattern) / sizeof (bitpattern[0]);
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k++) {
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*ibtr_p = compare = (bitpattern[k] << j);
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readback = *ibtr_p;
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if (readback != ~compare) {
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printf ("%s:%d: FPGA test fail: expected 0x%.8lx" " actual 0x%.8lx\n", __FUNCTION__, __LINE__, ~compare, readback);
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pass = 0;
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break;
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}
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}
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if (!pass)
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break;
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}
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if (!pass)
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break;
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}
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if (pass) {
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printf ("FPGA inverting bus test passed\n");
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print_fpga_revision ();
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} else {
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printf ("** FPGA inverting bus test failed\n");
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}
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return pass;
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}
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/*
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* Set the active-low FPGA reset signal.
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*/
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void fpga_reset (int assert)
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{
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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PRINTF ("%s:%d: RESET ", __FUNCTION__, __LINE__);
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if (assert) {
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immap->im_ioport.iop_pcdat &= ~(0x8000 >> FPGA_RESET_BIT_NUM);
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PRINTF ("asserted\n");
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} else {
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immap->im_ioport.iop_pcdat |= (0x8000 >> FPGA_RESET_BIT_NUM);
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PRINTF ("deasserted\n");
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}
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}
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/*
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* Initialize the SelectMap interface. We assume that the mode and the
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* initial state of all of the port pins have already been set!
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*/
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void fpga_selectmap_init (void)
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{
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PRINTF ("%s:%d: Initialize SelectMap interface\n", __FUNCTION__,
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__LINE__);
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fpga_pgm_fn (FALSE, FALSE, 0); /* make sure program pin is inactive */
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}
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/*
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* Initialize the fpga. Return 1 on success, 0 on failure.
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*/
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int gen860t_init_fpga (void)
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{
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int i;
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PRINTF ("%s:%d: Initialize FPGA interface (relocation offset = 0x%.8lx)\n", __FUNCTION__, __LINE__, gd->reloc_off);
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fpga_init (gd->reloc_off);
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fpga_selectmap_init ();
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for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
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PRINTF ("%s:%d: Adding fpga %d\n", __FUNCTION__, __LINE__, i);
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fpga_add (fpga_xilinx, &fpga[i]);
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}
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return 1;
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}
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/*
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* Set the FPGA's active-low SelectMap program line to the specified level
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*/
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int fpga_pgm_fn (int assert, int flush, int cookie)
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{
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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PRINTF ("%s:%d: FPGA PROGRAM ", __FUNCTION__, __LINE__);
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if (assert) {
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immap->im_ioport.iop_padat &=
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~(0x8000 >> FPGA_PROGRAM_BIT_NUM);
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PRINTF ("asserted\n");
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} else {
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immap->im_ioport.iop_padat |=
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(0x8000 >> FPGA_PROGRAM_BIT_NUM);
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PRINTF ("deasserted\n");
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}
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return assert;
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}
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/*
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* Test the state of the active-low FPGA INIT line. Return 1 on INIT
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* asserted (low).
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*/
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int fpga_init_fn (int cookie)
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{
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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PRINTF ("%s:%d: INIT check... ", __FUNCTION__, __LINE__);
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if (immap->im_cpm.cp_pbdat & (0x80000000 >> FPGA_INIT_BIT_NUM)) {
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PRINTF ("high\n");
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return 0;
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} else {
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PRINTF ("low\n");
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return 1;
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}
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}
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/*
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* Test the state of the active-high FPGA DONE pin
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*/
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int fpga_done_fn (int cookie)
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{
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volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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PRINTF ("%s:%d: DONE check... ", __FUNCTION__, __LINE__);
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if (immap->im_cpm.cp_pbdat & (0x80000000 >> FPGA_DONE_BIT_NUM)) {
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PRINTF ("high\n");
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return FPGA_SUCCESS;
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} else {
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PRINTF ("low\n");
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return FPGA_FAIL;
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}
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}
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/*
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* Read FPGA SelectMap data.
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*/
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int fpga_read_data_fn (unsigned char *data, int cookie)
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{
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vu_char *p = (vu_char *) SELECTMAP_BASE;
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*data = *p;
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#if 0
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PRINTF ("%s: Read 0x%x into 0x%p\n", __FUNCTION__, (int) data, data);
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#endif
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return (int) data;
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}
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/*
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* Write data to the FPGA SelectMap port
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*/
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int fpga_write_data_fn (unsigned char data, int flush, int cookie)
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{
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vu_char *p = (vu_char *) SELECTMAP_BASE;
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#if 0
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PRINTF ("%s: Write Data 0x%x\n", __FUNCTION__, (int) data);
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#endif
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*p = data;
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return (int) data;
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}
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/*
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* Abort and FPGA operation
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*/
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int fpga_abort_fn (int cookie)
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{
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PRINTF ("%s:%d: FPGA program sequence aborted\n",
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__FUNCTION__, __LINE__);
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return FPGA_FAIL;
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}
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/*
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* FPGA pre-configuration function. Just make sure that
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* FPGA reset is asserted to keep the FPGA from starting up after
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* configuration.
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*/
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int fpga_pre_config_fn (int cookie)
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{
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PRINTF ("%s:%d: FPGA pre-configuration\n", __FUNCTION__, __LINE__);
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fpga_reset (TRUE);
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return 0;
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}
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/*
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* FPGA post configuration function. Blip the FPGA reset line and then see if
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* the FPGA appears to be running.
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*/
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int fpga_post_config_fn (int cookie)
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{
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int rc;
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PRINTF ("%s:%d: FPGA post configuration\n", __FUNCTION__, __LINE__);
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fpga_reset (TRUE);
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udelay (1000);
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fpga_reset (FALSE);
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udelay (1000);
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/*
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* Use the FPGA,s inverting bus test register to do a simple test of the
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* processor interface.
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*/
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rc = test_fpga_ibtr ();
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return rc;
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}
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/*
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* Clock, chip select and write signal assert functions and error check
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* and busy functions. These are only stubs because the GEN860T selectmap
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* interface handles sequencing of control signals automatically (it uses
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* a memory-mapped interface to the FPGA SelectMap port). The design of
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* the interface guarantees that the SelectMap port cannot be overrun so
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* no busy check is needed. A configuration error is signalled by INIT
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* going low during configuration, so there is no need for a separate error
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* function.
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*/
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int fpga_clk_fn (int assert_clk, int flush, int cookie)
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{
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return assert_clk;
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}
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int fpga_cs_fn (int assert_cs, int flush, int cookie)
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{
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return assert_cs;
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}
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int fpga_wr_fn (int assert_write, int flush, int cookie)
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{
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return assert_write;
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}
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int fpga_err_fn (int cookie)
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{
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return 0;
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}
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int fpga_busy_fn (int cookie)
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{
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return 0;
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}
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#endif
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