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https://github.com/brain-hackers/u-boot-brain
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5c374c9ee1
The Hammerhead platform is built around a AVR32 32-bit microcontroller from Atmel. It offers versatile peripherals, such as ethernet, usb device, usb host etc. The board also incooperates a power supply and is a Power over Ethernet (PoE) Powered Device (PD). Additonally, a Cyclone III FPGA from Altera is integrated on the board. The FPGA is mapped into the 32-bit AVR memory bus. The FPGA offers two DDR2 SDRAM interfaces, which will cover even the most exceptional need of memory bandwidth. Together with the onboard video decoder the board is ready for video processing. For more information see: http:///www.miromico.com/hammerhead Signed-off-by: Julien May <mailinglist@miromico.ch> [haavard.skinnemoen@atmel.com: various small fixes and adaptions] Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
93 lines
2.5 KiB
C
93 lines
2.5 KiB
C
/*
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* Copyright (C) 2005-2006 Atmel Corporation
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/io.h>
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#include <asm/sections.h>
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#include <asm/sysreg.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/memory-map.h>
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#include "hsmc3.h"
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/* Sanity checks */
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#if (CFG_CLKDIV_CPU > CFG_CLKDIV_HSB) \
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|| (CFG_CLKDIV_HSB > CFG_CLKDIV_PBA) \
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|| (CFG_CLKDIV_HSB > CFG_CLKDIV_PBB)
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# error Constraint fCPU >= fHSB >= fPB{A,B} violated
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#endif
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#if defined(CONFIG_PLL) && ((CFG_PLL0_MUL < 1) || (CFG_PLL0_DIV < 1))
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# error Invalid PLL multiplier and/or divider
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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int cpu_init(void)
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{
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extern void _evba(void);
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gd->cpu_hz = CFG_OSC0_HZ;
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/* TODO: Move somewhere else, but needs to be run before we
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* increase the clock frequency. */
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hsmc3_writel(MODE0, 0x00031103);
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hsmc3_writel(CYCLE0, 0x000c000d);
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hsmc3_writel(PULSE0, 0x0b0a0906);
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hsmc3_writel(SETUP0, 0x00010002);
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clk_init();
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/* Update the CPU speed according to the PLL configuration */
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gd->cpu_hz = get_cpu_clk_rate();
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/* Set up the exception handler table and enable exceptions */
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sysreg_write(EVBA, (unsigned long)&_evba);
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asm volatile("csrf %0" : : "i"(SYSREG_EM_OFFSET));
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if(gclk_init)
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gclk_init();
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return 0;
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}
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void prepare_to_boot(void)
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{
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/* Flush both caches and the write buffer */
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asm volatile("cache %0[4], 010\n\t"
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"cache %0[0], 000\n\t"
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"sync 0" : : "r"(0) : "memory");
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}
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int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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/* This will reset the CPU core, caches, MMU and all internal busses */
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__builtin_mtdr(8, 1 << 13); /* set DC:DBE */
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__builtin_mtdr(8, 1 << 30); /* set DC:RES */
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/* Flush the pipeline before we declare it a failure */
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asm volatile("sub pc, pc, -4");
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return -1;
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}
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