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https://github.com/brain-hackers/u-boot-brain
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5c374c9ee1
The Hammerhead platform is built around a AVR32 32-bit microcontroller from Atmel. It offers versatile peripherals, such as ethernet, usb device, usb host etc. The board also incooperates a power supply and is a Power over Ethernet (PoE) Powered Device (PD). Additonally, a Cyclone III FPGA from Altera is integrated on the board. The FPGA is mapped into the 32-bit AVR memory bus. The FPGA offers two DDR2 SDRAM interfaces, which will cover even the most exceptional need of memory bandwidth. Together with the onboard video decoder the board is ready for video processing. For more information see: http:///www.miromico.com/hammerhead Signed-off-by: Julien May <mailinglist@miromico.ch> [haavard.skinnemoen@atmel.com: various small fixes and adaptions] Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
115 lines
2.7 KiB
C
115 lines
2.7 KiB
C
/*
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* Copyright (C) 2008 Miromico AG
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*
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* Mostly copied form atmel ATNGW100 sources
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include "../cpu/at32ap/at32ap700x/sm.h"
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#include <common.h>
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#include <asm/io.h>
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#include <asm/sdram.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/hmatrix.h>
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#include <asm/arch/memory-map.h>
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DECLARE_GLOBAL_DATA_PTR;
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static const struct sdram_config sdram_config = {
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.data_bits = SDRAM_DATA_32BIT,
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.row_bits = 13,
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.col_bits = 9,
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.bank_bits = 2,
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.cas = 3,
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.twr = 2,
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.trc = 7,
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.trp = 2,
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.trcd = 2,
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.tras = 5,
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.txsr = 5,
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/* 7.81 us */
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.refresh_period = (781 * (SDRAMC_BUS_HZ / 1000)) / 100000,
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};
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extern int macb_eth_initialize(int id, void *regs, unsigned int phy_addr);
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#ifdef CONFIG_CMD_NET
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int board_eth_init(bd_t *bis)
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{
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return macb_eth_initialize(0, (void *)MACB0_BASE, bis->bi_phy_id[0]);
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}
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#endif
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int board_early_init_f(void)
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{
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/* Enable SDRAM in the EBI mux */
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hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
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gpio_enable_ebi();
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gpio_enable_usart1();
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#if defined(CONFIG_MACB)
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gpio_enable_macb0();
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#endif
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#if defined(CONFIG_MMC)
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gpio_enable_mmci();
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#endif
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return 0;
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}
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phys_size_t initdram(int board_type)
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{
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unsigned long expected_size;
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unsigned long actual_size;
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void *sdram_base;
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sdram_base = map_physmem(EBI_SDRAM_BASE, EBI_SDRAM_SIZE, MAP_NOCACHE);
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expected_size = sdram_init(sdram_base, &sdram_config);
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actual_size = get_ram_size(sdram_base, expected_size);
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unmap_physmem(sdram_base, EBI_SDRAM_SIZE);
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if (expected_size != actual_size)
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printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
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actual_size >> 20, expected_size >> 20);
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return actual_size;
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}
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void board_init_info(void)
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{
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gd->bd->bi_phy_id[0] = 0x01;
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}
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void gclk_init(void)
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{
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/* Hammerhead boards uses GCLK3 as 25MHz output to ethernet PHY */
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/* Select GCLK3 peripheral function */
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gpio_select_periph_A(GPIO_PIN_PB29, 0);
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/* Enable GCLK3 with no input divider, from OSC0 (crystal) */
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sm_writel(PM_GCCTRL(3), SM_BIT(CEN));
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}
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