mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-04 17:23:45 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
184 lines
6.7 KiB
C
184 lines
6.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) Marvell International Ltd. and its affiliates
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*/
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#include <common.h>
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#include <spl.h>
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#include <asm/io.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/soc.h>
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#include "high_speed_env_spec.h"
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MV_SERDES_CHANGE_M_PHY serdes_change_m_phy[] = {
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/* SERDES TYPE, Low REG OFFS, Low REG VALUE, Hi REG OFS, Hi REG VALUE */
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{
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/* PEX: Change of Slew Rate port0 */
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SERDES_UNIT_PEX, 0x0,
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(0x0F << 16) | 0x2a21, 0x0, (0x0F << 16) | 0x2a21
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}, {
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/* PEX: Change PLL BW port0 */
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SERDES_UNIT_PEX, 0x0,
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(0x4F << 16) | 0x6219, 0x0, (0x4F << 16) | 0x6219
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}, {
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/* SATA: Slew rate change port 0 */
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SERDES_UNIT_SATA, 0x0083C, 0x8a31, 0x0083C, 0x8a31
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}, {
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/* SATA: Slew rate change port 0 */
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SERDES_UNIT_SATA, 0x00834, 0xc928, 0x00834, 0xc928
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}, {
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/* SATA: Slew rate change port 0 */
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SERDES_UNIT_SATA, 0x00838, 0x30f0, 0x00838, 0x30f0
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}, {
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/* SATA: Slew rate change port 0 */
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SERDES_UNIT_SATA, 0x00840, 0x30f5, 0x00840, 0x30f5
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}, {
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/* SGMII: FFE setting Port0 */
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SERDES_UNIT_SGMII0, 0x00E18, 0x989F, 0x00E18, 0x989F
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}, {
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/* SGMII: SELMUP and SELMUF Port0 */
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SERDES_UNIT_SGMII0, 0x00E38, 0x10FA, 0x00E38, 0x10FA
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}, {
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/* SGMII: Amplitude new setting gen2 Port3 */
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SERDES_UNIT_SGMII0, 0x00E34, 0xC968, 0x00E34, 0xC66C
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}, {
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/* QSGMII: Amplitude and slew rate change */
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SERDES_UNIT_QSGMII, 0x72E34, 0xaa58, 0x72E34, 0xaa58
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}, {
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/* QSGMII: SELMUP and SELMUF */
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SERDES_UNIT_QSGMII, 0x72e38, 0x10aF, 0x72e38, 0x10aF
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}, {
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/* QSGMII: 0x72e18 */
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SERDES_UNIT_QSGMII, 0x72e18, 0x98AC, 0x72e18, 0x98AC
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}, {
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/* Null terminated */
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SERDES_UNIT_UNCONNECTED, 0, 0
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}
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};
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MV_BIN_SERDES_CFG db88f78xx0_serdes_cfg[] = {
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/* Z1B */
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{MV_PEX_ROOT_COMPLEX, 0x32221111, 0x11111111,
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{PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
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0x0030, serdes_change_m_phy}, /* Default */
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{MV_PEX_ROOT_COMPLEX, 0x31211111, 0x11111111,
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{PEX_BUS_MODE_X1, PEX_BUS_MODE_X1, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
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0x0030, serdes_change_m_phy}, /* PEX module */
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/* Z1A */
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{MV_PEX_ROOT_COMPLEX, 0x32220000, 0x00000000,
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{PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED,
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PEX_BUS_DISABLED}, 0x0030, serdes_change_m_phy}, /* Default - Z1A */
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{MV_PEX_ROOT_COMPLEX, 0x31210000, 0x00000000,
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{PEX_BUS_DISABLED, PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_DISABLED},
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0x0030, serdes_change_m_phy} /* PEX module - Z1A */
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};
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MV_BIN_SERDES_CFG db88f78xx0rev2_serdes_cfg[] = {
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/* A0 */
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{MV_PEX_ROOT_COMPLEX, 0x33221111, 0x11111111,
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{PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
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0x0030, serdes_change_m_phy}, /* Default: No Pex module, PEX0 x1, disabled */
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{MV_PEX_ROOT_COMPLEX, 0x33211111, 0x11111111,
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{PEX_BUS_MODE_X1, PEX_BUS_MODE_X1, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
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0x0030, serdes_change_m_phy}, /* Pex module, PEX0 x1, PEX1 x1 */
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{MV_PEX_ROOT_COMPLEX, 0x33221111, 0x11111111,
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{PEX_BUS_MODE_X4, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
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0x0030, serdes_change_m_phy}, /* no Pex module, PEX0 x4, PEX1 disabled */
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{MV_PEX_ROOT_COMPLEX, 0x33211111, 0x11111111,
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{PEX_BUS_MODE_X4, PEX_BUS_MODE_X1, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
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0x0030, serdes_change_m_phy}, /* Pex module, PEX0 x4, PEX1 x1 */
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{MV_PEX_ROOT_COMPLEX, 0x11111111, 0x11111111,
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{PEX_BUS_MODE_X1, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
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0x0030, serdes_change_m_phy}, /* Pex module, PEX0 x1, PEX1 x4 */
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{MV_PEX_ROOT_COMPLEX, 0x11111111, 0x11111111,
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{PEX_BUS_MODE_X4, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
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0x0030, serdes_change_m_phy}, /* Pex module, PEX0 x4, PEX1 x4 */
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};
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MV_BIN_SERDES_CFG rd78460nas_serdes_cfg[] = {
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{MV_PEX_ROOT_COMPLEX, 0x00223001, 0x11111111,
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{PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
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0x0030, serdes_change_m_phy}, /* Default */
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{MV_PEX_ROOT_COMPLEX, 0x33320201, 0x11111111,
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{PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
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0x00f4, serdes_change_m_phy}, /* Switch module */
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};
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MV_BIN_SERDES_CFG rd78460_serdes_cfg[] = {
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{MV_PEX_ROOT_COMPLEX, 0x22321111, 0x00000000,
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{PEX_BUS_MODE_X4, PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED},
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0x0010, serdes_change_m_phy}, /* CPU0 */
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{MV_PEX_ROOT_COMPLEX, 0x00321111, 0x00000000,
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{PEX_BUS_MODE_X4, PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED},
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0x0010, serdes_change_m_phy} /* CPU1-3 */
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};
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MV_BIN_SERDES_CFG rd78460server_rev2_serdes_cfg[] = {
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{MV_PEX_ROOT_COMPLEX, 0x00321111, 0x00000000,
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{PEX_BUS_MODE_X4, PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED},
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0x0010, serdes_change_m_phy}, /* CPU0 */
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{MV_PEX_ROOT_COMPLEX, 0x00321111, 0x00000000,
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{PEX_BUS_MODE_X4, PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED},
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0x0010, serdes_change_m_phy} /* CPU1-3 */
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};
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MV_BIN_SERDES_CFG db78X60pcac_serdes_cfg[] = {
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{MV_PEX_END_POINT, 0x22321111, 0x00000000,
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{PEX_BUS_MODE_X4, PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED},
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0x0010, serdes_change_m_phy} /* Default */
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};
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MV_BIN_SERDES_CFG db78X60pcacrev2_serdes_cfg[] = {
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{MV_PEX_END_POINT, 0x23321111, 0x00000000,
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{PEX_BUS_MODE_X4, PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED},
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0x0010, serdes_change_m_phy} /* Default */
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};
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MV_BIN_SERDES_CFG fpga88f78xx0_serdes_cfg[] = {
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{MV_PEX_ROOT_COMPLEX, 0x00000000, 0x00000000,
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{PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED, PEX_BUS_DISABLED},
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0x0000, serdes_change_m_phy} /* No PEX in FPGA */
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};
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MV_BIN_SERDES_CFG db78X60amc_serdes_cfg[] = {
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{MV_PEX_ROOT_COMPLEX, 0x33111111, 0x00010001,
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{PEX_BUS_MODE_X4, PEX_BUS_MODE_X1, PEX_BUS_MODE_X1, PEX_BUS_MODE_X1},
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0x0030, serdes_change_m_phy} /* Default */
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};
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/*
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* ARMADA-XP CUSTOMER BOARD
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*/
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MV_BIN_SERDES_CFG rd78460customer_serdes_cfg[] = {
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{MV_PEX_ROOT_COMPLEX, 0x00223001, 0x11111111,
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{PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
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0x00000030, serdes_change_m_phy}, /* Default */
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{MV_PEX_ROOT_COMPLEX, 0x33320201, 0x11111111,
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{PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
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0x00000030, serdes_change_m_phy}, /* Switch module */
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};
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MV_BIN_SERDES_CFG rd78460AXP_GP_serdes_cfg[] = {
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{MV_PEX_ROOT_COMPLEX, 0x00223001, 0x11111111,
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{PEX_BUS_MODE_X1, PEX_BUS_DISABLED, PEX_BUS_MODE_X4, PEX_BUS_MODE_X4},
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0x0030, serdes_change_m_phy} /* Default */
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};
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MV_BIN_SERDES_CFG *serdes_info_tbl[] = {
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db88f78xx0_serdes_cfg,
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rd78460_serdes_cfg,
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db78X60pcac_serdes_cfg,
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fpga88f78xx0_serdes_cfg,
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db88f78xx0rev2_serdes_cfg,
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rd78460nas_serdes_cfg,
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db78X60amc_serdes_cfg,
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db78X60pcacrev2_serdes_cfg,
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rd78460server_rev2_serdes_cfg,
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rd78460AXP_GP_serdes_cfg,
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rd78460customer_serdes_cfg
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};
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u8 rd78460gp_twsi_dev[] = { 0x4C, 0x4D, 0x4E };
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u8 db88f78xx0rev2_twsi_dev[] = { 0x4C, 0x4D, 0x4E, 0x4F };
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