mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
250 lines
6.2 KiB
C
250 lines
6.2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
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*/
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#include <common.h>
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#include <usb.h>
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#include <asm/io.h>
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#include <asm/arch/imx-regs.h>
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#include <usb/ehci-ci.h>
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#include <errno.h>
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#include "ehci.h"
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#define USBCTRL_OTGBASE_OFFSET 0x600
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#define MX25_OTG_SIC_SHIFT 29
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#define MX25_OTG_SIC_MASK (0x3 << MX25_OTG_SIC_SHIFT)
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#define MX25_OTG_PM_BIT (1 << 24)
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#define MX25_OTG_PP_BIT (1 << 11)
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#define MX25_OTG_OCPOL_BIT (1 << 3)
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#define MX25_H1_SIC_SHIFT 21
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#define MX25_H1_SIC_MASK (0x3 << MX25_H1_SIC_SHIFT)
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#define MX25_H1_PP_BIT (1 << 18)
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#define MX25_H1_PM_BIT (1 << 16)
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#define MX25_H1_IPPUE_UP_BIT (1 << 7)
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#define MX25_H1_IPPUE_DOWN_BIT (1 << 6)
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#define MX25_H1_TLL_BIT (1 << 5)
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#define MX25_H1_USBTE_BIT (1 << 4)
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#define MX25_H1_OCPOL_BIT (1 << 2)
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#define MX31_OTG_SIC_SHIFT 29
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#define MX31_OTG_SIC_MASK (0x3 << MX31_OTG_SIC_SHIFT)
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#define MX31_OTG_PM_BIT (1 << 24)
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#define MX31_H2_SIC_SHIFT 21
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#define MX31_H2_SIC_MASK (0x3 << MX31_H2_SIC_SHIFT)
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#define MX31_H2_PM_BIT (1 << 16)
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#define MX31_H2_DT_BIT (1 << 5)
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#define MX31_H1_SIC_SHIFT 13
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#define MX31_H1_SIC_MASK (0x3 << MX31_H1_SIC_SHIFT)
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#define MX31_H1_PM_BIT (1 << 8)
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#define MX31_H1_DT_BIT (1 << 4)
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#define MX35_OTG_SIC_SHIFT 29
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#define MX35_OTG_SIC_MASK (0x3 << MX35_OTG_SIC_SHIFT)
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#define MX35_OTG_PM_BIT (1 << 24)
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#define MX35_OTG_PP_BIT (1 << 11)
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#define MX35_OTG_OCPOL_BIT (1 << 3)
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#define MX35_H1_SIC_SHIFT 21
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#define MX35_H1_SIC_MASK (0x3 << MX35_H1_SIC_SHIFT)
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#define MX35_H1_PP_BIT (1 << 18)
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#define MX35_H1_PM_BIT (1 << 16)
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#define MX35_H1_IPPUE_UP_BIT (1 << 7)
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#define MX35_H1_IPPUE_DOWN_BIT (1 << 6)
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#define MX35_H1_TLL_BIT (1 << 5)
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#define MX35_H1_USBTE_BIT (1 << 4)
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#define MX35_H1_OCPOL_BIT (1 << 2)
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static int mxc_set_usbcontrol(int port, unsigned int flags)
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{
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unsigned int v;
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v = readl(IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET);
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#if defined(CONFIG_MX25)
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switch (port) {
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case 0: /* OTG port */
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v &= ~(MX25_OTG_SIC_MASK | MX25_OTG_PM_BIT | MX25_OTG_PP_BIT |
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MX25_OTG_OCPOL_BIT);
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v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_OTG_SIC_SHIFT;
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if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
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v |= MX25_OTG_PM_BIT;
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if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
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v |= MX25_OTG_PP_BIT;
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if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
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v |= MX25_OTG_OCPOL_BIT;
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break;
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case 1: /* H1 port */
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v &= ~(MX25_H1_SIC_MASK | MX25_H1_PM_BIT | MX25_H1_PP_BIT |
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MX25_H1_OCPOL_BIT | MX25_H1_TLL_BIT |
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MX25_H1_USBTE_BIT | MX25_H1_IPPUE_DOWN_BIT |
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MX25_H1_IPPUE_UP_BIT);
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v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_H1_SIC_SHIFT;
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if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
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v |= MX25_H1_PM_BIT;
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if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
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v |= MX25_H1_PP_BIT;
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if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
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v |= MX25_H1_OCPOL_BIT;
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if (!(flags & MXC_EHCI_TTL_ENABLED))
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v |= MX25_H1_TLL_BIT;
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if (flags & MXC_EHCI_INTERNAL_PHY)
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v |= MX25_H1_USBTE_BIT;
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if (flags & MXC_EHCI_IPPUE_DOWN)
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v |= MX25_H1_IPPUE_DOWN_BIT;
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if (flags & MXC_EHCI_IPPUE_UP)
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v |= MX25_H1_IPPUE_UP_BIT;
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break;
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default:
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return -EINVAL;
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}
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#elif defined(CONFIG_MX31)
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switch (port) {
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case 0: /* OTG port */
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v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
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v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_OTG_SIC_SHIFT;
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if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
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v |= MX31_OTG_PM_BIT;
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break;
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case 1: /* H1 port */
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v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT | MX31_H1_DT_BIT);
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v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H1_SIC_SHIFT;
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if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
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v |= MX31_H1_PM_BIT;
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if (!(flags & MXC_EHCI_TTL_ENABLED))
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v |= MX31_H1_DT_BIT;
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break;
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case 2: /* H2 port */
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v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT | MX31_H2_DT_BIT);
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v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H2_SIC_SHIFT;
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if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
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v |= MX31_H2_PM_BIT;
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if (!(flags & MXC_EHCI_TTL_ENABLED))
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v |= MX31_H2_DT_BIT;
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break;
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default:
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return -EINVAL;
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}
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#elif defined(CONFIG_MX35)
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switch (port) {
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case 0: /* OTG port */
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v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT | MX35_OTG_PP_BIT |
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MX35_OTG_OCPOL_BIT);
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v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_OTG_SIC_SHIFT;
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if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
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v |= MX35_OTG_PM_BIT;
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if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
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v |= MX35_OTG_PP_BIT;
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if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
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v |= MX35_OTG_OCPOL_BIT;
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break;
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case 1: /* H1 port */
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v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_PP_BIT |
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MX35_H1_OCPOL_BIT | MX35_H1_TLL_BIT |
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MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT |
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MX35_H1_IPPUE_UP_BIT);
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v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_H1_SIC_SHIFT;
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if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
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v |= MX35_H1_PM_BIT;
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if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
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v |= MX35_H1_PP_BIT;
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if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
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v |= MX35_H1_OCPOL_BIT;
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if (!(flags & MXC_EHCI_TTL_ENABLED))
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v |= MX35_H1_TLL_BIT;
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if (flags & MXC_EHCI_INTERNAL_PHY)
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v |= MX35_H1_USBTE_BIT;
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if (flags & MXC_EHCI_IPPUE_DOWN)
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v |= MX35_H1_IPPUE_DOWN_BIT;
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if (flags & MXC_EHCI_IPPUE_UP)
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v |= MX35_H1_IPPUE_UP_BIT;
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break;
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default:
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return -EINVAL;
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}
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#else
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#error MXC EHCI USB driver not supported on this platform
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#endif
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writel(v, IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET);
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return 0;
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}
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int ehci_hcd_init(int index, enum usb_init_type init,
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struct ehci_hccr **hccr, struct ehci_hcor **hcor)
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{
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struct usb_ehci *ehci;
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#ifdef CONFIG_MX31
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struct clock_control_regs *sc_regs =
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(struct clock_control_regs *)CCM_BASE;
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__raw_readl(&sc_regs->ccmr);
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__raw_writel(__raw_readl(&sc_regs->ccmr) | (1 << 9), &sc_regs->ccmr) ;
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#endif
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udelay(80);
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ehci = (struct usb_ehci *)(IMX_USB_BASE +
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IMX_USB_PORT_OFFSET * CONFIG_MXC_USB_PORT);
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*hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
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*hcor = (struct ehci_hcor *)((uint32_t) *hccr +
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HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
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setbits_le32(&ehci->usbmode, CM_HOST);
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__raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
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mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS);
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#ifdef CONFIG_MX35
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/* Workaround for ENGcm11601 */
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__raw_writel(0, &ehci->sbuscfg);
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#endif
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udelay(10000);
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return 0;
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}
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/*
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* Destroy the appropriate control structures corresponding
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* the the EHCI host controller.
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*/
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int ehci_hcd_stop(int index)
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{
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return 0;
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}
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