Simon Glass 5c1b685e46 x86: Allow timer calibration to work on ivybridge ... Unfortunately MSR_FSB_FREQ is not available on this CPU, and the PIT method seems to take up to 50ms which is much too long. For this CPU we know the frequency, so add another special case for now. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>		2014-11-21 07:24:12 +01:00
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cpu	x86: use CONFIG_SYS_COREBOOT to descend into coreboot/ directory	2014-11-21 07:24:12 +01:00
dts	dm: x86: Convert coreboot serial to use driver model	2014-10-23 19:45:45 -06:00
include/asm	x86: Replace fill_processor_name() with cpu_get_name()	2014-11-21 07:24:12 +01:00
lib	x86: Allow timer calibration to work on ivybridge	2014-11-21 07:24:12 +01:00
config.mk	x86: Remove REALMODE_BASE which is no longer used	2014-11-21 07:24:08 +01:00
Kconfig	kconfig: move CONFIG_USE_PRIVATE_LIBGCC to Kconfig	2014-10-23 13:19:09 -04:00