mirror of
https://github.com/brain-hackers/u-boot-brain
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5bf39a96c2
This patch fixes some problems for the T3CORP board. Here the list of the changes: - Add 600-67 and 677 CPU frequency setting to chip_config command - Define CONFIG_DDR_RFDC_FIXED on t3corp: While using the "normal" auto calibration code, sometimes values for RFDC were picked (>= T3) that resulted in a non-working U-Boot (hang upon relocation, while running from SDRAM). With this optimized RFDC value we can force this register and use the auto-calibration code to setup the remaining calibration registers. - Increase sizes of FPGA chips selects - EBC timing updated OEN=3 for 66 MHz EBC speed - Change ext. IRQ2 setup to level-low active - Enable CONFIG_SYS_CFI_FLASH_STATUS_POLL By defining CONFIG_SYS_CFI_FLASH_STATUS_POLL, DQ7 is polled to detect the chip busy status. This is now used instead of the data toggle method which is used historically by default in the common CFI driver. With this change a problem with not written data is solved on this board, where a 32 byte block of data is still erased instead of filled with the correct content after these commands: => erase 0xfc100000 +0x1000000 .................................................................... done Erased 128 sectors => cp.b 0x100000 0xfc100000 0x1000000 Copy to Flash... done => cmp.b 0x100000 0xfc100000 0x1000000 byte at 0x00d0d6c0 (0x00) != byte at 0xfcd0d6c0 (0xff) Total of 12637888 bytes were the same Signed-off-by: Stefan Roese <sr@denx.de>
102 lines
3.1 KiB
ArmAsm
102 lines
3.1 KiB
ArmAsm
/*
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* (C) Copyright 2010
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <ppc_asm.tmpl>
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#include <config.h>
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#include <asm/mmu.h>
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/*
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* TLB TABLE
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*
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* This table is used by the cpu boot code to setup the initial tlb
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* entries. Rather than make broad assumptions in the cpu source tree,
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* this table lets each board set things up however they like.
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*
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* Pointer to the table is returned in r1
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*
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*/
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.section .bootpg,"ax"
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.globl tlbtab
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tlbtab:
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tlbtab_start
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/*
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* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to
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* use the speed up boot process. It is patched after relocation to
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* enable SA_I
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*/
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tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M,
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CONFIG_SYS_BOOT_BASE_ADDR, 4, AC_RWX | SA_G)
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/*
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* TLB entries for SDRAM are not needed on this platform.
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* They are dynamically generated in the DDR(2) detection
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* routine.
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*/
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#ifdef CONFIG_SYS_INIT_RAM_DCACHE
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/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
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tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0,
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AC_RWX | SA_G)
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#endif
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tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xc,
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AC_RW | SA_IG)
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tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x20000000, 0xc,
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AC_RW | SA_IG)
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tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xd,
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AC_RW | SA_IG)
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tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xd,
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AC_RW | SA_IG)
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tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xd,
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AC_RW | SA_IG)
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tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xd,
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AC_RW | SA_IG)
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tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xd,
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AC_RW | SA_IG)
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/* PCIe UTL register */
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tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x08010000, 0xc, AC_RW | SA_IG)
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/* TLB-entry for FPGA(s) */
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tlbentry(CONFIG_SYS_FPGA1_BASE, SZ_16M, CONFIG_SYS_FPGA1_BASE, 4,
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AC_RW | SA_IG)
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tlbentry(CONFIG_SYS_FPGA1_BASE + (16 << 20), SZ_16M,
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CONFIG_SYS_FPGA1_BASE + (16 << 20), 4, AC_RW | SA_IG)
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tlbentry(CONFIG_SYS_FPGA2_BASE, SZ_16M, CONFIG_SYS_FPGA2_BASE, 4,
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AC_RW | SA_IG)
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tlbentry(CONFIG_SYS_FPGA3_BASE, SZ_16M, CONFIG_SYS_FPGA3_BASE, 4,
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AC_RW | SA_IG)
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/* TLB-entry for OCM */
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tlbentry(CONFIG_SYS_OCM_BASE, SZ_1M, 0x00000000, 4,
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AC_RWX | SA_I)
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/* TLB-entry for Local Configuration registers => peripherals */
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tlbentry(CONFIG_SYS_LOCAL_CONF_REGS, SZ_16M,
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CONFIG_SYS_LOCAL_CONF_REGS, 4, AC_RWX | SA_IG)
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tlbtab_end
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