mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-10-01 00:50:43 +09:00
dc73483a12
commit1601dd97ed("davinci: omapl138_lcdk: increase PLL0 frequency") changed the PLL0 frequency to 456MHz, which is needed for the LCDC IP block. However, in doing so, it caused the PLLOUT clock to be outside of the allowable specifications given in the OMAP-L138 data sheet. (It says PLLOUT must be 600MHz max). It also uses a PLLM value outside of the range given in the TRM (it says PLLM must in the range 0 to 0x1f). So here is what we have currently: PLLOUT = 24 / (0 + 1) * (37 + 1) = 912MHz (out of spec) ^ ^ ^ CLKIN PREDIV PLLM (out of spec) input to PLLDIVn = 912 / (1 + 1) = 456MHz (desired result) ^ ^ PLLOUT POSTDIV This changes the PLLM value to 18 and the POSTDIV value to 0 so that PLLOUT is now within specification but we still get the desired result. PLLOUT = 24 / (0 + 1) * (18 + 1) = 456MHz (within spec) ^ ^ ^ CLKIN PREDIV PLLM input to PLLDIVn = 456 / (0 + 1) = 456MHz (desired result) ^ ^ PLLOUT POSTDIV Fixes:1601dd97ed("davinci: omapl138_lcdk: increase PLL0 frequency") Signed-off-by: David Lechner <david@lechnology.com> Reported-by: Sekhar Nori <nsekhar@ti.com> Tested-by: Sekhar Nori <nsekhar@ti.com>
45 lines
1.1 KiB
Plaintext
45 lines
1.1 KiB
Plaintext
CONFIG_ARM=y
|
|
CONFIG_ARCH_DAVINCI=y
|
|
CONFIG_SYS_TEXT_BASE=0xc1080000
|
|
CONFIG_TARGET_OMAPL138_LCDK=y
|
|
CONFIG_SYS_DA850_PLL0_POSTDIV=0
|
|
CONFIG_SYS_DA850_PLL1_PLLDIV3=0x8003
|
|
CONFIG_TI_COMMON_CMD_OPTIONS=y
|
|
CONFIG_SPL_LIBCOMMON_SUPPORT=y
|
|
CONFIG_SPL_LIBGENERIC_SUPPORT=y
|
|
CONFIG_SPL_MMC_SUPPORT=y
|
|
CONFIG_SPL_SERIAL_SUPPORT=y
|
|
CONFIG_SPL_NAND_SUPPORT=y
|
|
CONFIG_BOOTDELAY=3
|
|
CONFIG_LOGLEVEL=3
|
|
CONFIG_VERSION_VARIABLE=y
|
|
# CONFIG_DISPLAY_CPUINFO is not set
|
|
# CONFIG_DISPLAY_BOARDINFO is not set
|
|
CONFIG_BOARD_EARLY_INIT_F=y
|
|
CONFIG_SPL=y
|
|
CONFIG_SPL_BOARD_INIT=y
|
|
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0xb5
|
|
CONFIG_HUSH_PARSER=y
|
|
CONFIG_CRC32_VERIFY=y
|
|
# CONFIG_CMD_EEPROM is not set
|
|
# CONFIG_CMD_FLASH is not set
|
|
# CONFIG_CMD_GPIO is not set
|
|
CONFIG_CMD_NAND=y
|
|
# CONFIG_CMD_SETEXPR is not set
|
|
CONFIG_CMD_DIAG=y
|
|
CONFIG_CMD_UBI=y
|
|
CONFIG_ENV_IS_IN_NAND=y
|
|
CONFIG_NET_RANDOM_ETHADDR=y
|
|
CONFIG_BOOTP_DNS=y
|
|
CONFIG_NAND=y
|
|
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
|
|
CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y
|
|
CONFIG_SYS_NAND_U_BOOT_OFFS=0x28000
|
|
CONFIG_SPL_NAND_SIMPLE=y
|
|
CONFIG_SPI_FLASH=y
|
|
CONFIG_SPI_FLASH_STMICRO=y
|
|
CONFIG_SPI_FLASH_WINBOND=y
|
|
CONFIG_SYS_NS16550=y
|
|
CONFIG_DAVINCI_SPI=y
|
|
CONFIG_OF_LIBFDT=y
|