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![Patrice Chotard](/assets/img/avatar_default.png)
Since 'commitf4fcba5c5b
("clk: implement clk_set_defaults()")' STM32F4 family board can't boot. Above patch calls clk_set_rate() for all nodes with assigned-clock-rates property. Clock driver for STM32F family doesn't implement .set_rate callback which make clk_set_defaults() exit on error and prevent board to boot. Fixes:f4fcba5c5b
("clk: implement clk_set_defaults()") Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
483 lines
13 KiB
C
483 lines
13 KiB
C
/*
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* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
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* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <clk-uclass.h>
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#include <dm.h>
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#include <stm32_rcc.h>
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#include <asm/io.h>
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#include <asm/arch/stm32.h>
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#include <asm/arch/stm32_pwr.h>
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#include <dt-bindings/mfd/stm32f7-rcc.h>
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#define RCC_CR_HSION BIT(0)
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#define RCC_CR_HSEON BIT(16)
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#define RCC_CR_HSERDY BIT(17)
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#define RCC_CR_HSEBYP BIT(18)
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#define RCC_CR_CSSON BIT(19)
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#define RCC_CR_PLLON BIT(24)
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#define RCC_CR_PLLRDY BIT(25)
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#define RCC_CR_PLLSAION BIT(28)
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#define RCC_CR_PLLSAIRDY BIT(29)
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#define RCC_PLLCFGR_PLLM_MASK GENMASK(5, 0)
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#define RCC_PLLCFGR_PLLN_MASK GENMASK(14, 6)
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#define RCC_PLLCFGR_PLLP_MASK GENMASK(17, 16)
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#define RCC_PLLCFGR_PLLQ_MASK GENMASK(27, 24)
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#define RCC_PLLCFGR_PLLSRC BIT(22)
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#define RCC_PLLCFGR_PLLM_SHIFT 0
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#define RCC_PLLCFGR_PLLN_SHIFT 6
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#define RCC_PLLCFGR_PLLP_SHIFT 16
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#define RCC_PLLCFGR_PLLQ_SHIFT 24
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#define RCC_CFGR_AHB_PSC_MASK GENMASK(7, 4)
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#define RCC_CFGR_APB1_PSC_MASK GENMASK(12, 10)
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#define RCC_CFGR_APB2_PSC_MASK GENMASK(15, 13)
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#define RCC_CFGR_SW0 BIT(0)
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#define RCC_CFGR_SW1 BIT(1)
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#define RCC_CFGR_SW_MASK GENMASK(1, 0)
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#define RCC_CFGR_SW_HSI 0
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#define RCC_CFGR_SW_HSE RCC_CFGR_SW0
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#define RCC_CFGR_SW_PLL RCC_CFGR_SW1
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#define RCC_CFGR_SWS0 BIT(2)
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#define RCC_CFGR_SWS1 BIT(3)
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#define RCC_CFGR_SWS_MASK GENMASK(3, 2)
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#define RCC_CFGR_SWS_HSI 0
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#define RCC_CFGR_SWS_HSE RCC_CFGR_SWS0
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#define RCC_CFGR_SWS_PLL RCC_CFGR_SWS1
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#define RCC_CFGR_HPRE_SHIFT 4
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#define RCC_CFGR_PPRE1_SHIFT 10
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#define RCC_CFGR_PPRE2_SHIFT 13
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#define RCC_PLLCFGR_PLLSAIN_MASK GENMASK(14, 6)
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#define RCC_PLLCFGR_PLLSAIP_MASK GENMASK(17, 16)
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#define RCC_PLLSAICFGR_PLLSAIN_SHIFT 6
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#define RCC_PLLSAICFGR_PLLSAIP_SHIFT 16
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#define RCC_PLLSAICFGR_PLLSAIP_4 BIT(16)
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#define RCC_PLLSAICFGR_PLLSAIQ_4 BIT(26)
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#define RCC_PLLSAICFGR_PLLSAIR_2 BIT(29)
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#define RCC_DCKCFGRX_CK48MSEL BIT(27)
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#define RCC_DCKCFGRX_SDMMC1SEL BIT(28)
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#define RCC_DCKCFGR2_SDMMC2SEL BIT(29)
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/*
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* RCC AHB1ENR specific definitions
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*/
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#define RCC_AHB1ENR_ETHMAC_EN BIT(25)
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#define RCC_AHB1ENR_ETHMAC_TX_EN BIT(26)
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#define RCC_AHB1ENR_ETHMAC_RX_EN BIT(27)
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/*
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* RCC APB1ENR specific definitions
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*/
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#define RCC_APB1ENR_TIM2EN BIT(0)
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#define RCC_APB1ENR_PWREN BIT(28)
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/*
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* RCC APB2ENR specific definitions
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*/
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#define RCC_APB2ENR_SYSCFGEN BIT(14)
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#define RCC_APB2ENR_SAI1EN BIT(22)
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enum periph_clock {
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TIMER2_CLOCK_CFG,
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};
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static const struct stm32_clk_info stm32f4_clk_info = {
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/* 180 MHz */
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.sys_pll_psc = {
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.pll_n = 360,
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.pll_p = 2,
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.pll_q = 8,
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.ahb_psc = AHB_PSC_1,
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.apb1_psc = APB_PSC_4,
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.apb2_psc = APB_PSC_2,
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},
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.has_overdrive = false,
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.v2 = false,
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};
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static const struct stm32_clk_info stm32f7_clk_info = {
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/* 200 MHz */
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.sys_pll_psc = {
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.pll_n = 400,
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.pll_p = 2,
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.pll_q = 8,
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.ahb_psc = AHB_PSC_1,
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.apb1_psc = APB_PSC_4,
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.apb2_psc = APB_PSC_2,
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},
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.has_overdrive = true,
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.v2 = true,
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};
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struct stm32_clk {
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struct stm32_rcc_regs *base;
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struct stm32_pwr_regs *pwr_regs;
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struct stm32_clk_info info;
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unsigned long hse_rate;
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};
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static int configure_clocks(struct udevice *dev)
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{
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struct stm32_clk *priv = dev_get_priv(dev);
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struct stm32_rcc_regs *regs = priv->base;
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struct stm32_pwr_regs *pwr = priv->pwr_regs;
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struct pll_psc *sys_pll_psc = &priv->info.sys_pll_psc;
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u32 pllsaicfgr = 0;
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/* Reset RCC configuration */
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setbits_le32(®s->cr, RCC_CR_HSION);
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writel(0, ®s->cfgr); /* Reset CFGR */
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clrbits_le32(®s->cr, (RCC_CR_HSEON | RCC_CR_CSSON
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| RCC_CR_PLLON | RCC_CR_PLLSAION));
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writel(0x24003010, ®s->pllcfgr); /* Reset value from RM */
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clrbits_le32(®s->cr, RCC_CR_HSEBYP);
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writel(0, ®s->cir); /* Disable all interrupts */
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/* Configure for HSE+PLL operation */
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setbits_le32(®s->cr, RCC_CR_HSEON);
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while (!(readl(®s->cr) & RCC_CR_HSERDY))
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;
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setbits_le32(®s->cfgr, ((
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sys_pll_psc->ahb_psc << RCC_CFGR_HPRE_SHIFT)
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| (sys_pll_psc->apb1_psc << RCC_CFGR_PPRE1_SHIFT)
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| (sys_pll_psc->apb2_psc << RCC_CFGR_PPRE2_SHIFT)));
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/* Configure the main PLL */
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setbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLSRC); /* pll source HSE */
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clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLM_MASK,
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sys_pll_psc->pll_m << RCC_PLLCFGR_PLLM_SHIFT);
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clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLN_MASK,
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sys_pll_psc->pll_n << RCC_PLLCFGR_PLLN_SHIFT);
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clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLP_MASK,
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((sys_pll_psc->pll_p >> 1) - 1) << RCC_PLLCFGR_PLLP_SHIFT);
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clrsetbits_le32(®s->pllcfgr, RCC_PLLCFGR_PLLQ_MASK,
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sys_pll_psc->pll_q << RCC_PLLCFGR_PLLQ_SHIFT);
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/* Configure the SAI PLL to get a 48 MHz source */
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pllsaicfgr = RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIQ_4 |
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RCC_PLLSAICFGR_PLLSAIP_4;
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pllsaicfgr |= 192 << RCC_PLLSAICFGR_PLLSAIN_SHIFT;
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writel(pllsaicfgr, ®s->pllsaicfgr);
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/* Enable the main PLL */
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setbits_le32(®s->cr, RCC_CR_PLLON);
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while (!(readl(®s->cr) & RCC_CR_PLLRDY))
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;
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if (priv->info.v2) { /*stm32f7 case */
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/* select PLLSAI as 48MHz clock source */
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setbits_le32(®s->dckcfgr2, RCC_DCKCFGRX_CK48MSEL);
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/* select 48MHz as SDMMC1 clock source */
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clrbits_le32(®s->dckcfgr2, RCC_DCKCFGRX_SDMMC1SEL);
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/* select 48MHz as SDMMC2 clock source */
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clrbits_le32(®s->dckcfgr2, RCC_DCKCFGR2_SDMMC2SEL);
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} else { /* stm32f4 case */
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/* select PLLSAI as 48MHz clock source */
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setbits_le32(®s->dckcfgr, RCC_DCKCFGRX_CK48MSEL);
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/* select 48MHz as SDMMC1 clock source */
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clrbits_le32(®s->dckcfgr, RCC_DCKCFGRX_SDMMC1SEL);
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}
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/* Enable the SAI PLL */
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setbits_le32(®s->cr, RCC_CR_PLLSAION);
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while (!(readl(®s->cr) & RCC_CR_PLLSAIRDY))
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;
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setbits_le32(®s->apb1enr, RCC_APB1ENR_PWREN);
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if (priv->info.has_overdrive) {
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/*
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* Enable high performance mode
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* System frequency up to 200 MHz
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*/
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setbits_le32(&pwr->cr1, PWR_CR1_ODEN);
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/* Infinite wait! */
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while (!(readl(&pwr->csr1) & PWR_CSR1_ODRDY))
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;
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/* Enable the Over-drive switch */
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setbits_le32(&pwr->cr1, PWR_CR1_ODSWEN);
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/* Infinite wait! */
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while (!(readl(&pwr->csr1) & PWR_CSR1_ODSWRDY))
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;
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}
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stm32_flash_latency_cfg(5);
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clrbits_le32(®s->cfgr, (RCC_CFGR_SW0 | RCC_CFGR_SW1));
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setbits_le32(®s->cfgr, RCC_CFGR_SW_PLL);
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while ((readl(®s->cfgr) & RCC_CFGR_SWS_MASK) !=
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RCC_CFGR_SWS_PLL)
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;
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/* gate the SAI clock, needed for MMC 1&2 clocks */
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setbits_le32(®s->apb2enr, RCC_APB2ENR_SAI1EN);
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#ifdef CONFIG_ETH_DESIGNWARE
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/* gate the SYSCFG clock, needed to set RMII ethernet interface */
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setbits_le32(®s->apb2enr, RCC_APB2ENR_SYSCFGEN);
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#endif
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return 0;
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}
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static unsigned long stm32_clk_pll48clk_rate(struct stm32_clk *priv,
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u32 sysclk)
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{
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struct stm32_rcc_regs *regs = priv->base;
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u16 pllq, pllm, pllsain, pllsaip;
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bool pllsai;
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pllq = (readl(®s->pllcfgr) & RCC_PLLCFGR_PLLQ_MASK)
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>> RCC_PLLCFGR_PLLQ_SHIFT;
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if (priv->info.v2) /*stm32f7 case */
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pllsai = readl(®s->dckcfgr2) & RCC_DCKCFGRX_CK48MSEL;
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else
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pllsai = readl(®s->dckcfgr) & RCC_DCKCFGRX_CK48MSEL;
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if (pllsai) {
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/* PLL48CLK is selected from PLLSAI, get PLLSAI value */
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pllm = (readl(®s->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
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pllsain = ((readl(®s->pllsaicfgr) & RCC_PLLCFGR_PLLSAIN_MASK)
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>> RCC_PLLSAICFGR_PLLSAIN_SHIFT);
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pllsaip = ((((readl(®s->pllsaicfgr) & RCC_PLLCFGR_PLLSAIP_MASK)
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>> RCC_PLLSAICFGR_PLLSAIP_SHIFT) + 1) << 1);
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return ((priv->hse_rate / pllm) * pllsain) / pllsaip;
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}
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/* PLL48CLK is selected from PLLQ */
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return sysclk / pllq;
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}
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static unsigned long stm32_clk_get_rate(struct clk *clk)
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{
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struct stm32_clk *priv = dev_get_priv(clk->dev);
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struct stm32_rcc_regs *regs = priv->base;
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u32 sysclk = 0;
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u32 shift = 0;
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u16 pllm, plln, pllp;
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/* Prescaler table lookups for clock computation */
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u8 ahb_psc_table[16] = {
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0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9
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};
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u8 apb_psc_table[8] = {
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0, 0, 0, 0, 1, 2, 3, 4
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};
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if ((readl(®s->cfgr) & RCC_CFGR_SWS_MASK) ==
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RCC_CFGR_SWS_PLL) {
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pllm = (readl(®s->pllcfgr) & RCC_PLLCFGR_PLLM_MASK);
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plln = ((readl(®s->pllcfgr) & RCC_PLLCFGR_PLLN_MASK)
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>> RCC_PLLCFGR_PLLN_SHIFT);
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pllp = ((((readl(®s->pllcfgr) & RCC_PLLCFGR_PLLP_MASK)
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>> RCC_PLLCFGR_PLLP_SHIFT) + 1) << 1);
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sysclk = ((priv->hse_rate / pllm) * plln) / pllp;
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} else {
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return -EINVAL;
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}
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switch (clk->id) {
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/*
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* AHB CLOCK: 3 x 32 bits consecutive registers are used :
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* AHB1, AHB2 and AHB3
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*/
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case STM32F7_AHB1_CLOCK(GPIOA) ... STM32F7_AHB3_CLOCK(QSPI):
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shift = ahb_psc_table[(
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(readl(®s->cfgr) & RCC_CFGR_AHB_PSC_MASK)
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>> RCC_CFGR_HPRE_SHIFT)];
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return sysclk >>= shift;
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/* APB1 CLOCK */
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case STM32F7_APB1_CLOCK(TIM2) ... STM32F7_APB1_CLOCK(UART8):
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shift = apb_psc_table[(
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(readl(®s->cfgr) & RCC_CFGR_APB1_PSC_MASK)
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>> RCC_CFGR_PPRE1_SHIFT)];
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return sysclk >>= shift;
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/* APB2 CLOCK */
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case STM32F7_APB2_CLOCK(TIM1) ... STM32F7_APB2_CLOCK(LTDC):
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/*
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* particular case for SDMMC1 and SDMMC2 :
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* 48Mhz source clock can be from main PLL or from
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* SAI PLL
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*/
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switch (clk->id) {
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case STM32F7_APB2_CLOCK(SDMMC1):
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if (readl(®s->dckcfgr2) & RCC_DCKCFGRX_SDMMC1SEL)
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/* System clock is selected as SDMMC1 clock */
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return sysclk;
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else
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return stm32_clk_pll48clk_rate(priv, sysclk);
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break;
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case STM32F7_APB2_CLOCK(SDMMC2):
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if (readl(®s->dckcfgr2) & RCC_DCKCFGR2_SDMMC2SEL)
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/* System clock is selected as SDMMC2 clock */
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return sysclk;
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else
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return stm32_clk_pll48clk_rate(priv, sysclk);
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break;
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}
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shift = apb_psc_table[(
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(readl(®s->cfgr) & RCC_CFGR_APB2_PSC_MASK)
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>> RCC_CFGR_PPRE2_SHIFT)];
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return sysclk >>= shift;
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default:
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pr_err("clock index %ld out of range\n", clk->id);
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return -EINVAL;
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}
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}
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static ulong stm32_set_rate(struct clk *clk, ulong rate)
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{
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return 0;
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}
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static int stm32_clk_enable(struct clk *clk)
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{
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struct stm32_clk *priv = dev_get_priv(clk->dev);
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struct stm32_rcc_regs *regs = priv->base;
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u32 offset = clk->id / 32;
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u32 bit_index = clk->id % 32;
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debug("%s: clkid = %ld, offset from AHB1ENR is %d, bit_index = %d\n",
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__func__, clk->id, offset, bit_index);
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setbits_le32(®s->ahb1enr + offset, BIT(bit_index));
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return 0;
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}
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void clock_setup(int peripheral)
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{
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switch (peripheral) {
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case TIMER2_CLOCK_CFG:
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setbits_le32(&STM32_RCC->apb1enr, RCC_APB1ENR_TIM2EN);
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break;
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default:
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break;
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}
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}
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static int stm32_clk_probe(struct udevice *dev)
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{
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struct ofnode_phandle_args args;
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struct udevice *fixed_clock_dev = NULL;
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struct clk clk;
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int err;
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debug("%s\n", __func__);
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struct stm32_clk *priv = dev_get_priv(dev);
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fdt_addr_t addr;
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addr = dev_read_addr(dev);
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if (addr == FDT_ADDR_T_NONE)
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return -EINVAL;
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priv->base = (struct stm32_rcc_regs *)addr;
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switch (dev_get_driver_data(dev)) {
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case STM32F4:
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memcpy(&priv->info, &stm32f4_clk_info,
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sizeof(struct stm32_clk_info));
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break;
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case STM32F7:
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memcpy(&priv->info, &stm32f7_clk_info,
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sizeof(struct stm32_clk_info));
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break;
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default:
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return -EINVAL;
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}
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/* retrieve HSE frequency (external oscillator) */
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err = uclass_get_device_by_name(UCLASS_CLK, "clk-hse",
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&fixed_clock_dev);
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if (err) {
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pr_err("Can't find fixed clock (%d)", err);
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return err;
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}
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err = clk_request(fixed_clock_dev, &clk);
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if (err) {
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pr_err("Can't request %s clk (%d)", fixed_clock_dev->name,
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err);
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return err;
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}
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/*
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* set pllm factor accordingly to the external oscillator
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* frequency (HSE). For STM32F4 and STM32F7, we want VCO
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* freq at 1MHz
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* if input PLL frequency is 25Mhz, divide it by 25
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*/
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clk.id = 0;
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priv->hse_rate = clk_get_rate(&clk);
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if (priv->hse_rate < 1000000) {
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pr_err("%s: unexpected HSE clock rate = %ld \"n", __func__,
|
|
priv->hse_rate);
|
|
return -EINVAL;
|
|
}
|
|
|
|
priv->info.sys_pll_psc.pll_m = priv->hse_rate / 1000000;
|
|
|
|
if (priv->info.has_overdrive) {
|
|
err = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0,
|
|
&args);
|
|
if (err) {
|
|
debug("%s: can't find syscon device (%d)\n", __func__,
|
|
err);
|
|
return err;
|
|
}
|
|
|
|
priv->pwr_regs = (struct stm32_pwr_regs *)ofnode_get_addr(args.node);
|
|
}
|
|
|
|
configure_clocks(dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int stm32_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
|
|
{
|
|
debug("%s(clk=%p)\n", __func__, clk);
|
|
|
|
if (args->args_count != 2) {
|
|
debug("Invaild args_count: %d\n", args->args_count);
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (args->args_count)
|
|
clk->id = args->args[1];
|
|
else
|
|
clk->id = 0;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct clk_ops stm32_clk_ops = {
|
|
.of_xlate = stm32_clk_of_xlate,
|
|
.enable = stm32_clk_enable,
|
|
.get_rate = stm32_clk_get_rate,
|
|
.set_rate = stm32_set_rate,
|
|
};
|
|
|
|
U_BOOT_DRIVER(stm32fx_clk) = {
|
|
.name = "stm32fx_rcc_clock",
|
|
.id = UCLASS_CLK,
|
|
.ops = &stm32_clk_ops,
|
|
.probe = stm32_clk_probe,
|
|
.priv_auto_alloc_size = sizeof(struct stm32_clk),
|
|
.flags = DM_FLAG_PRE_RELOC,
|
|
};
|