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https://github.com/brain-hackers/u-boot-brain
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![Masahiro Yamada](/assets/img/avatar_default.png)
This SoC is too old. It is difficult to maintain any longer. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
277 lines
5.4 KiB
C
277 lines
5.4 KiB
C
/*
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* Copyright (C) 2012-2015 Panasonic Corporation
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* Copyright (C) 2015-2017 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <fdt_support.h>
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#include <fdtdec.h>
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#include <linux/errno.h>
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#include <linux/sizes.h>
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#include "sg-regs.h"
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#include "soc-info.h"
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#define pr_warn(fmt, args...) printf(fmt, ##args)
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#define pr_err(fmt, args...) printf(fmt, ##args)
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DECLARE_GLOBAL_DATA_PTR;
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struct uniphier_memif_data {
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unsigned int soc_id;
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unsigned long sparse_ch1_base;
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int have_ch2;
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};
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static const struct uniphier_memif_data uniphier_memif_data[] = {
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{
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.soc_id = UNIPHIER_LD4_ID,
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.sparse_ch1_base = 0xc0000000,
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},
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{
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.soc_id = UNIPHIER_PRO4_ID,
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.sparse_ch1_base = 0xa0000000,
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},
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{
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.soc_id = UNIPHIER_SLD8_ID,
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.sparse_ch1_base = 0xc0000000,
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},
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{
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.soc_id = UNIPHIER_PRO5_ID,
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.sparse_ch1_base = 0xc0000000,
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},
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{
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.soc_id = UNIPHIER_PXS2_ID,
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.sparse_ch1_base = 0xc0000000,
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.have_ch2 = 1,
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},
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{
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.soc_id = UNIPHIER_LD6B_ID,
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.sparse_ch1_base = 0xc0000000,
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.have_ch2 = 1,
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},
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{
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.soc_id = UNIPHIER_LD11_ID,
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.sparse_ch1_base = 0xc0000000,
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},
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{
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.soc_id = UNIPHIER_LD20_ID,
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.sparse_ch1_base = 0xc0000000,
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.have_ch2 = 1,
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},
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{
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.soc_id = UNIPHIER_PXS3_ID,
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.sparse_ch1_base = 0xc0000000,
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.have_ch2 = 1,
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},
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};
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UNIPHIER_DEFINE_SOCDATA_FUNC(uniphier_get_memif_data, uniphier_memif_data)
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struct uniphier_dram_map {
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unsigned long base;
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unsigned long size;
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};
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static int uniphier_memconf_decode(struct uniphier_dram_map *dram_map)
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{
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const struct uniphier_memif_data *data;
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unsigned long size;
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u32 val;
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data = uniphier_get_memif_data();
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if (!data) {
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pr_err("unsupported SoC\n");
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return -EINVAL;
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}
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val = readl(SG_MEMCONF);
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/* set up ch0 */
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dram_map[0].base = CONFIG_SYS_SDRAM_BASE;
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switch (val & SG_MEMCONF_CH0_SZ_MASK) {
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case SG_MEMCONF_CH0_SZ_64M:
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size = SZ_64M;
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break;
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case SG_MEMCONF_CH0_SZ_128M:
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size = SZ_128M;
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break;
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case SG_MEMCONF_CH0_SZ_256M:
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size = SZ_256M;
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break;
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case SG_MEMCONF_CH0_SZ_512M:
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size = SZ_512M;
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break;
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case SG_MEMCONF_CH0_SZ_1G:
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size = SZ_1G;
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break;
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default:
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pr_err("error: invalid value is set to MEMCONF ch0 size\n");
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return -EINVAL;
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}
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if ((val & SG_MEMCONF_CH0_NUM_MASK) == SG_MEMCONF_CH0_NUM_2)
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size *= 2;
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dram_map[0].size = size;
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/* set up ch1 */
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dram_map[1].base = dram_map[0].base + size;
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if (val & SG_MEMCONF_SPARSEMEM) {
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if (dram_map[1].base > data->sparse_ch1_base) {
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pr_warn("Sparse mem is enabled, but ch0 and ch1 overlap\n");
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pr_warn("Only ch0 is available\n");
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dram_map[1].base = 0;
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return 0;
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}
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dram_map[1].base = data->sparse_ch1_base;
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}
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switch (val & SG_MEMCONF_CH1_SZ_MASK) {
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case SG_MEMCONF_CH1_SZ_64M:
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size = SZ_64M;
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break;
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case SG_MEMCONF_CH1_SZ_128M:
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size = SZ_128M;
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break;
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case SG_MEMCONF_CH1_SZ_256M:
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size = SZ_256M;
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break;
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case SG_MEMCONF_CH1_SZ_512M:
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size = SZ_512M;
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break;
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case SG_MEMCONF_CH1_SZ_1G:
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size = SZ_1G;
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break;
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default:
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pr_err("error: invalid value is set to MEMCONF ch1 size\n");
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return -EINVAL;
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}
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if ((val & SG_MEMCONF_CH1_NUM_MASK) == SG_MEMCONF_CH1_NUM_2)
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size *= 2;
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dram_map[1].size = size;
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if (!data->have_ch2 || val & SG_MEMCONF_CH2_DISABLE)
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return 0;
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/* set up ch2 */
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dram_map[2].base = dram_map[1].base + size;
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switch (val & SG_MEMCONF_CH2_SZ_MASK) {
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case SG_MEMCONF_CH2_SZ_64M:
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size = SZ_64M;
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break;
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case SG_MEMCONF_CH2_SZ_128M:
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size = SZ_128M;
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break;
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case SG_MEMCONF_CH2_SZ_256M:
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size = SZ_256M;
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break;
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case SG_MEMCONF_CH2_SZ_512M:
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size = SZ_512M;
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break;
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case SG_MEMCONF_CH2_SZ_1G:
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size = SZ_1G;
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break;
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default:
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pr_err("error: invalid value is set to MEMCONF ch2 size\n");
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return -EINVAL;
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}
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if ((val & SG_MEMCONF_CH2_NUM_MASK) == SG_MEMCONF_CH2_NUM_2)
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size *= 2;
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dram_map[2].size = size;
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return 0;
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}
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int dram_init(void)
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{
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struct uniphier_dram_map dram_map[3] = {};
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int ret, i;
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gd->ram_size = 0;
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ret = uniphier_memconf_decode(dram_map);
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if (ret)
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return ret;
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for (i = 0; i < ARRAY_SIZE(dram_map); i++) {
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if (!dram_map[i].size)
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break;
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/*
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* U-Boot relocates itself to the tail of the memory region,
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* but it does not expect sparse memory. We use the first
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* contiguous chunk here.
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*/
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if (i > 0 && dram_map[i - 1].base + dram_map[i - 1].size <
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dram_map[i].base)
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break;
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gd->ram_size += dram_map[i].size;
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}
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return 0;
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}
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int dram_init_banksize(void)
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{
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struct uniphier_dram_map dram_map[3] = {};
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int i;
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uniphier_memconf_decode(dram_map);
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for (i = 0; i < ARRAY_SIZE(dram_map); i++) {
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if (i >= ARRAY_SIZE(gd->bd->bi_dram))
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break;
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gd->bd->bi_dram[i].start = dram_map[i].base;
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gd->bd->bi_dram[i].size = dram_map[i].size;
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}
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return 0;
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}
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#ifdef CONFIG_OF_BOARD_SETUP
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/*
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* The DRAM PHY requires 64 byte scratch area in each DRAM channel
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* for its dynamic PHY training feature.
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*/
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int ft_board_setup(void *fdt, bd_t *bd)
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{
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unsigned long rsv_addr;
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const unsigned long rsv_size = 64;
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int i, ret;
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if (uniphier_get_soc_id() != UNIPHIER_LD20_ID)
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return 0;
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for (i = 0; i < ARRAY_SIZE(gd->bd->bi_dram); i++) {
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if (!gd->bd->bi_dram[i].size)
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continue;
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rsv_addr = gd->bd->bi_dram[i].start + gd->bd->bi_dram[i].size;
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rsv_addr -= rsv_size;
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ret = fdt_add_mem_rsv(fdt, rsv_addr, rsv_size);
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if (ret)
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return -ENOSPC;
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printf(" Reserved memory region for DRAM PHY training: addr=%lx size=%lx\n",
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rsv_addr, rsv_size);
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}
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return 0;
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}
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#endif
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