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![Tom Rini](/assets/img/avatar_default.png)
As part of testing booting Linux kernels on Rockchip devices, it was discovered by Ziyuan Xu and Sandy Patterson that we had multiple and for some cases incomplete isb definitions. This was causing a failure to boot of the Linux kernel. In order to solve this problem as well as cover any corner cases that we may also have had a number of changes are made in order to consolidate things. First, <asm/barriers.h> now becomes the source of isb/dsb/dmb definitions. This however introduces another complexity. Due to needing to build SPL for 32bit tegra with -march=armv4 we need to borrow the __LINUX_ARM_ARCH__ logic from the Linux Kernel in a more complete form. Move this from arch/arm/lib/Makefile to arch/arm/Makefile and add a comment about it. Now that we can always know what the target CPU is capable off we can get always do the correct thing for the barrier. The final part of this is that need to be consistent everywhere and call isb()/dsb()/dmb() and NOT call ISB/DSB/DMB in some cases and the function names in others. Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Acked-by: Ziyuan Xu <xzy.xu@rock-chips.com> Acked-by: Sandy Patterson <apatterson@sightlogix.com> Reported-by: Ziyuan Xu <xzy.xu@rock-chips.com> Reported-by: Sandy Patterson <apatterson@sightlogix.com> Signed-off-by: Tom Rini <trini@konsulko.com>
40 lines
958 B
C
40 lines
958 B
C
/*
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* DRAM init helper functions
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*
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* (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/barriers.h>
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#include <asm/io.h>
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#include <asm/arch/dram.h>
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/*
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* Wait up to 1s for value to be set in given part of reg.
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*/
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void mctl_await_completion(u32 *reg, u32 mask, u32 val)
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{
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unsigned long tmo = timer_get_us() + 1000000;
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while ((readl(reg) & mask) != val) {
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if (timer_get_us() > tmo)
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panic("Timeout initialising DRAM\n");
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}
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}
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/*
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* Test if memory at offset offset matches memory at begin of DRAM
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*/
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bool mctl_mem_matches(u32 offset)
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{
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/* Try to write different values to RAM at two addresses */
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writel(0, CONFIG_SYS_SDRAM_BASE);
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writel(0xaa55aa55, (ulong)CONFIG_SYS_SDRAM_BASE + offset);
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dsb();
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/* Check if the same value is actually observed when reading back */
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return readl(CONFIG_SYS_SDRAM_BASE) ==
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readl((ulong)CONFIG_SYS_SDRAM_BASE + offset);
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}
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