mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-19 16:38:53 +09:00
![Tom Rini](/assets/img/avatar_default.png)
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
328 lines
7.3 KiB
C
328 lines
7.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2014 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <command.h>
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#include <i2c.h>
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#include <netdev.h>
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#include <linux/compiler.h>
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#include <asm/mmu.h>
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#include <asm/processor.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_law.h>
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#include <asm/fsl_serdes.h>
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#include <asm/fsl_liodn.h>
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#include <fm_eth.h>
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#include "t102xrdb.h"
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#ifdef CONFIG_TARGET_T1024RDB
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#include "cpld.h"
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#elif defined(CONFIG_TARGET_T1023RDB)
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#include <i2c.h>
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#include <mmc.h>
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#endif
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#include "../common/sleep.h"
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_TARGET_T1023RDB
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enum {
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GPIO1_SD_SEL = 0x00020000, /* GPIO1_14, 0: eMMC, 1:SD/MMC */
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GPIO1_EMMC_SEL,
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GPIO3_GET_VERSION, /* GPIO3_4/5, 00:RevB, 01: RevC */
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GPIO3_BRD_VER_MASK = 0x0c000000,
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GPIO3_OFFSET = 0x2000,
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I2C_GET_BANK,
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I2C_SET_BANK0,
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I2C_SET_BANK4,
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};
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#endif
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int checkboard(void)
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{
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struct cpu_type *cpu = gd->arch.cpu;
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static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"};
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ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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u32 srds_s1;
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srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
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srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
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printf("Board: %sRDB, ", cpu->name);
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#if defined(CONFIG_TARGET_T1024RDB)
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printf("Board rev: 0x%02x CPLD ver: 0x%02x, ",
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CPLD_READ(hw_ver), CPLD_READ(sw_ver));
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#elif defined(CONFIG_TARGET_T1023RDB)
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printf("Rev%c, ", t1023rdb_ctrl(GPIO3_GET_VERSION) + 'B');
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#endif
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printf("boot from ");
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#ifdef CONFIG_SDCARD
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puts("SD/MMC\n");
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#elif CONFIG_SPIFLASH
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puts("SPI\n");
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#elif defined(CONFIG_TARGET_T1024RDB)
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u8 reg;
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reg = CPLD_READ(flash_csr);
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if (reg & CPLD_BOOT_SEL) {
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puts("NAND\n");
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} else {
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reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
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printf("NOR vBank%d\n", reg);
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}
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#elif defined(CONFIG_TARGET_T1023RDB)
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#ifdef CONFIG_NAND
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puts("NAND\n");
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#else
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printf("NOR vBank%d\n", t1023rdb_ctrl(I2C_GET_BANK));
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#endif
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#endif
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puts("SERDES Reference Clocks:\n");
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if (srds_s1 == 0x95)
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printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]);
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else
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printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[0], freq[1]);
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return 0;
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}
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#ifdef CONFIG_TARGET_T1024RDB
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static void board_mux_lane(void)
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{
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ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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u32 srds_prtcl_s1;
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u8 reg = CPLD_READ(misc_ctl_status);
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srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
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FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
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srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
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if (srds_prtcl_s1 == 0x95) {
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/* Route Lane B to PCIE */
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CPLD_WRITE(misc_ctl_status, reg & ~CPLD_PCIE_SGMII_MUX);
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} else {
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/* Route Lane B to SGMII */
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CPLD_WRITE(misc_ctl_status, reg | CPLD_PCIE_SGMII_MUX);
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}
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CPLD_WRITE(boot_override, CPLD_OVERRIDE_MUX_EN);
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}
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#endif
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int board_early_init_f(void)
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{
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#if defined(CONFIG_DEEP_SLEEP)
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if (is_warm_boot())
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fsl_dp_disable_console();
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#endif
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return 0;
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}
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int board_early_init_r(void)
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{
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#ifdef CONFIG_SYS_FLASH_BASE
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const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
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int flash_esel = find_tlb_idx((void *)flashbase, 1);
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/*
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* Remap Boot flash region to caching-inhibited
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* so that flash can be erased properly.
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*/
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/* Flush d-cache and invalidate i-cache of any FLASH data */
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flush_dcache();
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invalidate_icache();
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if (flash_esel == -1) {
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/* very unlikely unless something is messed up */
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puts("Error: Could not find TLB for FLASH BASE\n");
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flash_esel = 2; /* give our best effort to continue */
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} else {
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/* invalidate existing TLB entry for flash + promjet */
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disable_tlb(flash_esel);
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}
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set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, flash_esel, BOOKE_PAGESZ_256M, 1);
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#endif
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#ifdef CONFIG_TARGET_T1024RDB
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board_mux_lane();
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#endif
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return 0;
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}
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unsigned long get_board_sys_clk(void)
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{
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return CONFIG_SYS_CLK_FREQ;
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}
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unsigned long get_board_ddr_clk(void)
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{
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return CONFIG_DDR_CLK_FREQ;
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}
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#ifdef CONFIG_TARGET_T1024RDB
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void board_reset(void)
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{
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CPLD_WRITE(reset_ctl1, CPLD_LBMAP_RESET);
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}
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#endif
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int misc_init_r(void)
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{
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return 0;
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}
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int ft_board_setup(void *blob, bd_t *bd)
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{
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phys_addr_t base;
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phys_size_t size;
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ft_cpu_setup(blob, bd);
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base = env_get_bootm_low();
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size = env_get_bootm_size();
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fdt_fixup_memory(blob, (u64)base, (u64)size);
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#ifdef CONFIG_PCI
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pci_of_setup(blob, bd);
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#endif
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fdt_fixup_liodn(blob);
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fsl_fdt_fixup_dr_usb(blob, bd);
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#ifdef CONFIG_SYS_DPAA_FMAN
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fdt_fixup_fman_ethernet(blob);
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fdt_fixup_board_enet(blob);
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#endif
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#ifdef CONFIG_TARGET_T1023RDB
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if (t1023rdb_ctrl(GPIO3_GET_VERSION) > 0)
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fdt_enable_nor(blob);
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#endif
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return 0;
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}
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#ifdef CONFIG_TARGET_T1023RDB
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/* Enable NOR flash for RevC */
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static void fdt_enable_nor(void *blob)
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{
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int nodeoff = fdt_node_offset_by_compatible(blob, 0, "cfi-flash");
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if (nodeoff >= 0)
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fdt_status_okay(blob, nodeoff);
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else
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printf("WARNING unable to set status for NOR\n");
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}
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int board_mmc_getcd(struct mmc *mmc)
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{
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ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
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u32 val = in_be32(&pgpio->gpdat);
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/* GPIO1_14, 0: eMMC, 1: SD/MMC */
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val &= GPIO1_SD_SEL;
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return val ? -1 : 1;
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}
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int board_mmc_getwp(struct mmc *mmc)
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{
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ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
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u32 val = in_be32(&pgpio->gpdat);
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val &= GPIO1_SD_SEL;
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return val ? -1 : 0;
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}
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static u32 t1023rdb_ctrl(u32 ctrl_type)
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{
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ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
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ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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u32 val, orig_bus = i2c_get_bus_num();
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u8 tmp;
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switch (ctrl_type) {
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case GPIO1_SD_SEL:
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val = in_be32(&pgpio->gpdat);
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val |= GPIO1_SD_SEL;
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out_be32(&pgpio->gpdat, val);
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setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
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break;
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case GPIO1_EMMC_SEL:
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val = in_be32(&pgpio->gpdat);
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val &= ~GPIO1_SD_SEL;
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out_be32(&pgpio->gpdat, val);
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setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL);
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break;
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case GPIO3_GET_VERSION:
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pgpio = (ccsr_gpio_t *)(CONFIG_SYS_MPC85xx_GPIO_ADDR
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+ GPIO3_OFFSET);
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val = in_be32(&pgpio->gpdat);
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val = ((val & GPIO3_BRD_VER_MASK) >> 26) & 0x3;
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if (val == 0x3) /* GPIO3_4/5 not used on RevB */
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val = 0;
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return val;
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case I2C_GET_BANK:
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i2c_set_bus_num(I2C_PCA6408_BUS_NUM);
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i2c_read(I2C_PCA6408_ADDR, 0, 1, &tmp, 1);
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tmp &= 0x7;
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tmp = ((tmp & 1) << 2) | (tmp & 2) | ((tmp & 4) >> 2);
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i2c_set_bus_num(orig_bus);
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return tmp;
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case I2C_SET_BANK0:
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i2c_set_bus_num(I2C_PCA6408_BUS_NUM);
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tmp = 0x0;
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i2c_write(I2C_PCA6408_ADDR, 1, 1, &tmp, 1);
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tmp = 0xf8;
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i2c_write(I2C_PCA6408_ADDR, 3, 1, &tmp, 1);
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/* asserting HRESET_REQ */
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out_be32(&gur->rstcr, 0x2);
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break;
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case I2C_SET_BANK4:
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i2c_set_bus_num(I2C_PCA6408_BUS_NUM);
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tmp = 0x1;
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i2c_write(I2C_PCA6408_ADDR, 1, 1, &tmp, 1);
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tmp = 0xf8;
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i2c_write(I2C_PCA6408_ADDR, 3, 1, &tmp, 1);
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out_be32(&gur->rstcr, 0x2);
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break;
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default:
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break;
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}
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return 0;
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}
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static int switch_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
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char * const argv[])
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{
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if (argc < 2)
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return CMD_RET_USAGE;
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if (!strcmp(argv[1], "bank0"))
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t1023rdb_ctrl(I2C_SET_BANK0);
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else if (!strcmp(argv[1], "bank4") || !strcmp(argv[1], "altbank"))
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t1023rdb_ctrl(I2C_SET_BANK4);
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else if (!strcmp(argv[1], "sd"))
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t1023rdb_ctrl(GPIO1_SD_SEL);
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else if (!strcmp(argv[1], "emmc"))
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t1023rdb_ctrl(GPIO1_EMMC_SEL);
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else
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return CMD_RET_USAGE;
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return 0;
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}
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U_BOOT_CMD(
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switch, 2, 0, switch_cmd,
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"for bank0/bank4/sd/emmc switch control in runtime",
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"command (e.g. switch bank4)"
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);
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#endif
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