mirror of
https://github.com/brain-hackers/u-boot-brain
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97 lines
2.7 KiB
C
97 lines
2.7 KiB
C
/*
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* (C) Copyright 2008 Dmitry Rakhchev, EmCraft Systems, rda@emcraft.com
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*
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* Developed for DENX Software Engineering GmbH
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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/* This test attempts to verify board GDC. A scratch register tested, then
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* simple memory test (get_ram_size()) run over GDC memory.
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*/
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#include <post.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define GDC_SCRATCH_REG 0xC1FF8044
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#define GDC_VERSION_REG 0xC1FF8084
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#define GDC_RAM_START 0xC0000000
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#define GDC_RAM_END 0xC2000000
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#if CONFIG_POST & CONFIG_SYS_POST_BSPEC4
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static int gdc_test_reg_one(uint value)
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{
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int ret;
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uint read_value;
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/* write test pattern */
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out_be32((void *)GDC_SCRATCH_REG, value);
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/* read other location (protect against data lines capacity) */
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ret = in_be32((void *)GDC_RAM_START);
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/* verify test pattern */
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read_value = in_be32((void *)GDC_SCRATCH_REG);
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if (read_value != value) {
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post_log("GDC SCRATCH test failed write %08X, read %08X\n",
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value, read_value);
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}
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return (read_value != value);
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}
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/* Verify GDC, get memory size */
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int gdc_post_test(int flags)
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{
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uint old_value;
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int ret = 0;
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post_log("\n");
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old_value = in_be32((void *)GDC_SCRATCH_REG);
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/*
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* GPIOC2 register behaviour: the LIME graphics processor has a
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* maximum of 5 GPIO ports that can be used in this hardware
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* configuration. Thus only the bits for these 5 GPIOs can be
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* activated in the GPIOC2 register. All other bits will always be
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* read as zero.
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*/
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if (gdc_test_reg_one(0x00150015))
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ret = 1;
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if (gdc_test_reg_one(0x000A000A))
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ret = 1;
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out_be32((void *)GDC_SCRATCH_REG, old_value);
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old_value = in_be32((void *)GDC_VERSION_REG);
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post_log("GDC chip version %u.%u, year %04X\n",
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(old_value >> 8) & 0xFF, old_value & 0xFF,
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(old_value >> 16) & 0xFFFF);
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old_value = get_ram_size((void *)GDC_RAM_START,
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GDC_RAM_END - GDC_RAM_START);
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post_log("GDC RAM size: %d bytes\n", old_value);
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return ret;
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}
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#endif /* CONFIG_POST & CONFIG_SYS_POST_BSPEC4 */
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