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https://github.com/brain-hackers/u-boot-brain
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![wdenk](/assets/img/avatar_default.png)
- remove trailing white space, trailing empty lines, C++ comments, etc. - split cmd_boot.c (separate cmd_bdinfo.c and cmd_load.c) * Patches by Kenneth Johansson, 25 Jun 2003: - major rework of command structure (work done mostly by Michal Cendrowski and Joakim Kristiansen)
231 lines
5.2 KiB
C
231 lines
5.2 KiB
C
/*
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* (C) Copyright 2002
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* John W. Linville, linville@tuxdriver.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include "i8259.h"
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#undef IRQ_DEBUG
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#ifdef IRQ_DEBUG
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#define PRINTF(fmt,args...) printf (fmt ,##args)
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#else
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#define PRINTF(fmt,args...)
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#endif
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static inline unsigned char read_byte(volatile unsigned char* from)
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{
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int x;
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asm volatile ("lbz %0,%1\n eieio" : "=r" (x) : "m" (*from));
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return (unsigned char)x;
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}
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static inline void write_byte(volatile unsigned char *to, int x)
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{
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asm volatile ("stb %1,%0\n eieio" : "=m" (*to) : "r" (x));
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}
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static inline unsigned long read_long_little(volatile unsigned long *from)
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{
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unsigned long x;
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asm volatile ("lwbrx %0,0,%1\n eieio\n sync" : "=r" (x) : "r" (from), "m"(*from));
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return (unsigned long)x;
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}
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#ifdef out8
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#undef out8
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#endif
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#ifdef in8
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#undef in8
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#endif
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#define out8(addr, byte) write_byte(0xFE000000 | addr, byte)
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#define in8(addr) read_byte(0xFE000000 | addr)
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/*
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* This contains the irq mask for both 8259A irq controllers,
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*/
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static char cached_imr[2] = {0xff, 0xff};
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#define cached_imr1 (cached_imr[0])
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#define cached_imr2 (cached_imr[1])
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void i8259_init(void)
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{
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char dummy;
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PRINTF("Initializing Interrupt controller\n");
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/* init master interrupt controller */
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out8(0x20, 0x11); /* 0x19); /###* Start init sequence */
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out8(0x21, 0x00); /* Vector base */
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out8(0x21, 0x04); /* edge tiggered, Cascade (slave) on IRQ2 */
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out8(0x21, 0x11); /* was: 0x01); /###* Select 8086 mode */
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/* init slave interrupt controller */
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out8(0xA0, 0x11); /* 0x19); /###* Start init sequence */
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out8(0xA1, 0x08); /* Vector base */
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out8(0xA1, 0x02); /* edge triggered, Cascade (slave) on IRQ2 */
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out8(0xA1, 0x11); /* was: 0x01); /###* Select 8086 mode */
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/* always read ISR */
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out8(0x20, 0x0B);
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dummy = in8(ISR_1);
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out8(0xA0, 0x0B);
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dummy = in8(ISR_2);
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/* out8(0x43, 0x30); */
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/* out8(0x40, 0); */
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/* out8(0x40, 0); */
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/* out8(0x43, 0x70); */
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/* out8(0x41, 0); */
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/* out8(0x41, 0); */
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/* out8(0x43, 0xb0); */
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/* out8(0x42, 0); */
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/* out8(0x42, 0); */
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/* Mask all interrupts */
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out8(IMR_2, cached_imr2);
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out8(IMR_1, cached_imr1);
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i8259_unmask_irq(2);
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#if 0
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{
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int i;
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for (i=0; i<16; i++)
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{
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i8259_unmask_irq(i);
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}
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}
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#endif
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}
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static volatile char *pci_intack = (void *)0xFEF00000;
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int i8259_irq(void)
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{
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int irq;
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irq = read_long_little(pci_intack) & 0xff;
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if (irq==7) {
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/*
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* This may be a spurious interrupt.
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*
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* Read the interrupt status register (ISR). If the most
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* significant bit is not set then there is no valid
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* interrupt.
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*/
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if(~in8(0x20)&0x80) {
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irq = -1;
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}
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}
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return irq;
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}
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int i8259_get_irq(struct pt_regs *regs)
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{
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unsigned char irq;
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/*
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* Perform an interrupt acknowledge cycle on controller 1
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*/
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out8(OCW3_1, 0x0C); /* prepare for poll */
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irq = in8(IPL_1) & 7;
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if (irq == 2) {
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/*
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* Interrupt is cascaded so perform interrupt
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* acknowledge on controller 2
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*/
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out8(OCW3_2, 0x0C); /* prepare for poll */
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irq = (in8(IPL_2) & 7) + 8;
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if (irq == 15) {
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/*
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* This may be a spurious interrupt
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*
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* Read the interrupt status register. If the most
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* significant bit is not set then there is no valid
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* interrupt
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*/
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out8(OCW3_2, 0x0b);
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if (~(in8(ISR_2) & 0x80)) {
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return -1;
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}
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}
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} else if (irq == 7) {
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/*
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* This may be a spurious interrupt
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*
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* Read the interrupt status register. If the most
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* significant bit is not set then there is no valid
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* interrupt
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*/
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out8(OCW3_1, 0x0b);
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if (~(in8(ISR_1) & 0x80)) {
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return -1;
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}
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}
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return irq;
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}
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/*
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* Careful! The 8259A is a fragile beast, it pretty
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* much _has_ to be done exactly like this (mask it
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* first, _then_ send the EOI, and the order of EOI
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* to the two 8259s is important!
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*/
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void i8259_mask_and_ack(int irq)
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{
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if (irq > 7) {
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cached_imr2 |= (1 << (irq - 8));
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in8(IMR_2); /* DUMMY */
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out8(IMR_2, cached_imr2);
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out8(OCW2_2, 0x20); /* Non-specific EOI */
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out8(OCW2_1, 0x20); /* Non-specific EOI to cascade */
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} else {
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cached_imr1 |= (1 << irq);
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in8(IMR_1); /* DUMMY */
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out8(IMR_1, cached_imr1);
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out8(OCW2_1, 0x20); /* Non-specific EOI */
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}
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}
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void i8259_mask_irq(int irq)
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{
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if (irq & 8) {
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cached_imr2 |= (1 << (irq & 7));
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out8(IMR_2, cached_imr2);
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} else {
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cached_imr1 |= (1 << irq);
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out8(IMR_1, cached_imr1);
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}
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}
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void i8259_unmask_irq(int irq)
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{
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if (irq & 8) {
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cached_imr2 &= ~(1 << (irq & 7));
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out8(IMR_2, cached_imr2);
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} else {
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cached_imr1 &= ~(1 << irq);
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out8(IMR_1, cached_imr1);
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}
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}
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