mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-27 12:28:52 +09:00
65dd74a674
Implement SDRAM init using the Memory Reference Code (mrc.bin) provided in the board directory and the SDRAM SPD information in the device tree. This also needs the Intel Management Engine (me.bin) to work. Binary blobs everywhere: so far we have MRC, ME and microcode. SDRAM init works by setting up various parameters and calling the MRC. This in turn does some sort of magic to work out how much memory there is and the timing parameters to use. It also sets up the DRAM controllers. When the MRC returns, we use the information it provides to map out the available memory in U-Boot. U-Boot normally moves itself to the top of RAM. On x86 the RAM is not generally contiguous, and anyway some RAM may be above 4GB which doesn't work in 32-bit mode. So we relocate to the top of the largest block of RAM we can find below 4GB. Memory above 4GB is accessible with special functions (see physmem). It would be possible to build U-Boot in 64-bit mode but this wouldn't necessarily provide any more memory, since the largest block is often below 4GB. Anyway U-Boot doesn't need huge amounts of memory - even a very large ramdisk seldom exceeds 100-200MB. U-Boot has support for booting 64-bit kernels directly so this does not pose a limitation in that area. Also there are probably parts of U-Boot that will not work correctly in 64-bit mode. The MRC is one. There is some work remaining in this area. Since memory init is very slow (over 500ms) it is possible to save the parameters in SPI flash to speed it up next time. Suspend/resume support is not fully implemented, or at least it is not efficient. With this patch, link boots to a prompt. Signed-off-by: Simon Glass <sjg@chromium.org>
90 lines
1.9 KiB
C
90 lines
1.9 KiB
C
/*
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* From Coreboot src/northbridge/intel/sandybridge/report_platform.c
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*
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* Copyright (C) 2012 Google Inc.
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <common.h>
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#include <asm/cpu.h>
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#include <asm/pci.h>
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#include <asm/arch/pch.h>
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static void report_cpu_info(void)
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{
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char cpu_string[CPU_MAX_NAME_LEN], *cpu_name;
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const char *mode[] = {"NOT ", ""};
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struct cpuid_result cpuidr;
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int vt, txt, aes;
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u32 index;
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index = 0x80000000;
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cpuidr = cpuid(index);
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if (cpuidr.eax < 0x80000004) {
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strcpy(cpu_string, "Platform info not available");
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cpu_name = cpu_string;
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} else {
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cpu_name = cpu_get_name(cpu_string);
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}
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cpuidr = cpuid(1);
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debug("CPU id(%x): %s\n", cpuidr.eax, cpu_name);
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aes = (cpuidr.ecx & (1 << 25)) ? 1 : 0;
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txt = (cpuidr.ecx & (1 << 6)) ? 1 : 0;
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vt = (cpuidr.ecx & (1 << 5)) ? 1 : 0;
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debug("AES %ssupported, TXT %ssupported, VT %ssupported\n",
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mode[aes], mode[txt], mode[vt]);
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}
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/* The PCI id name match comes from Intel document 472178 */
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static struct {
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u16 dev_id;
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const char *dev_name;
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} pch_table[] = {
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{0x1E41, "Desktop Sample"},
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{0x1E42, "Mobile Sample"},
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{0x1E43, "SFF Sample"},
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{0x1E44, "Z77"},
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{0x1E45, "H71"},
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{0x1E46, "Z75"},
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{0x1E47, "Q77"},
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{0x1E48, "Q75"},
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{0x1E49, "B75"},
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{0x1E4A, "H77"},
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{0x1E53, "C216"},
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{0x1E55, "QM77"},
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{0x1E56, "QS77"},
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{0x1E58, "UM77"},
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{0x1E57, "HM77"},
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{0x1E59, "HM76"},
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{0x1E5D, "HM75"},
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{0x1E5E, "HM70"},
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{0x1E5F, "NM70"},
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};
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static void report_pch_info(void)
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{
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const char *pch_type = "Unknown";
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int i;
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u16 dev_id;
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uint8_t rev_id;
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dev_id = pci_read_config16(PCH_LPC_DEV, 2);
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for (i = 0; i < ARRAY_SIZE(pch_table); i++) {
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if (pch_table[i].dev_id == dev_id) {
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pch_type = pch_table[i].dev_name;
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break;
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}
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}
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rev_id = pci_read_config8(PCH_LPC_DEV, 8);
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debug("PCH type: %s, device id: %x, rev id %x\n", pch_type, dev_id,
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rev_id);
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}
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void report_platform_info(void)
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{
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report_cpu_info();
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report_pch_info();
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}
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