mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-28 05:43:57 +09:00
5aeab3bf5e
J721e has two instances of Cadence USB3 controller. Add DT nodes for the same. USB0 is configured to device mode and USB1 is configured to host mode. For now only high speed mode is supported. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
328 lines
6.9 KiB
Plaintext
328 lines
6.9 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
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*/
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#include <dt-bindings/dma/k3-udma.h>
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#include <dt-bindings/net/ti-dp83867.h>
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/ {
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chosen {
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stdout-path = "serial2:115200n8";
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tick-timer = &timer1;
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};
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aliases {
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ethernet0 = &cpsw_port1;
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};
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};
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&cbass_main{
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u-boot,dm-spl;
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};
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&cbass_mcu_wakeup {
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u-boot,dm-spl;
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timer1: timer@40400000 {
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compatible = "ti,omap5430-timer";
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reg = <0x0 0x40400000 0x0 0x80>;
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ti,timer-alwon;
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clock-frequency = <25000000>;
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u-boot,dm-spl;
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};
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mcu_conf: scm_conf@40f00000 {
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compatible = "syscon", "simple-mfd";
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reg = <0x0 0x40f00000 0x0 0x20000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0x40f00000 0x20000>;
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phy_sel: cpsw-phy-sel@4040 {
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compatible = "ti,am654-cpsw-phy-sel";
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reg = <0x4040 0x4>;
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reg-names = "gmii-sel";
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};
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};
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cbass_mcu_navss: mcu_navss {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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dma-coherent;
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dma-ranges;
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ranges;
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ti,sci-dev-id = <232>;
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u-boot,dm-spl;
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mcu_ringacc: ringacc@2b800000 {
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compatible = "ti,am654-navss-ringacc";
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reg = <0x0 0x2b800000 0x0 0x400000>,
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<0x0 0x2b000000 0x0 0x400000>,
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<0x0 0x28590000 0x0 0x100>,
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<0x0 0x2a500000 0x0 0x40000>;
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reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
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ti,num-rings = <286>;
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ti,sci-rm-range-gp-rings = <0x1>; /* GP ring range */
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <235>;
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u-boot,dm-spl;
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};
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mcu_udmap: udmap@31150000 {
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compatible = "ti,j721e-navss-mcu-udmap";
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reg = <0x0 0x285c0000 0x0 0x100>,
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<0x0 0x2a800000 0x0 0x40000>,
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<0x0 0x2aa00000 0x0 0x40000>;
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reg-names = "gcfg", "rchanrt", "tchanrt";
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#dma-cells = <3>;
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ti,ringacc = <&mcu_ringacc>;
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ti,psil-base = <0x6000>;
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <236>;
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ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
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<0x0f>; /* TX_HCHAN */
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ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
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<0x0b>; /* RX_HCHAN */
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ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
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u-boot,dm-spl;
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};
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};
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mcu_cpsw: ethernet@046000000 {
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compatible = "ti,j721e-cpsw-nuss";
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#address-cells = <2>;
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#size-cells = <2>;
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reg = <0x0 0x46000000 0x0 0x200000>;
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reg-names = "cpsw_nuss";
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ranges;
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dma-coherent;
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clocks = <&k3_clks 18 22>;
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clock-names = "fck";
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power-domains = <&k3_pds 18 TI_SCI_PD_EXCLUSIVE>;
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ti,psil-base = <0x7000>;
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cpsw-phy-sel = <&phy_sel>;
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dmas = <&mcu_udmap &mcu_cpsw 0 UDMA_DIR_TX>,
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<&mcu_udmap &mcu_cpsw 1 UDMA_DIR_TX>,
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<&mcu_udmap &mcu_cpsw 2 UDMA_DIR_TX>,
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<&mcu_udmap &mcu_cpsw 3 UDMA_DIR_TX>,
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<&mcu_udmap &mcu_cpsw 4 UDMA_DIR_TX>,
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<&mcu_udmap &mcu_cpsw 5 UDMA_DIR_TX>,
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<&mcu_udmap &mcu_cpsw 6 UDMA_DIR_TX>,
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<&mcu_udmap &mcu_cpsw 7 UDMA_DIR_TX>,
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<&mcu_udmap &mcu_cpsw 0 UDMA_DIR_RX>;
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dma-names = "tx0", "tx1", "tx2", "tx3",
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"tx4", "tx5", "tx6", "tx7",
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"rx";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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host: host@0 {
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reg = <0>;
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ti,label = "host";
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};
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cpsw_port1: port@1 {
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reg = <1>;
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ti,mac-only;
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ti,label = "port1";
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ti,syscon-efuse = <&mcu_conf 0x200>;
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};
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};
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davinci_mdio: mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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bus_freq = <1000000>;
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};
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cpts {
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clocks = <&k3_clks 18 2>;
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clock-names = "cpts";
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interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "cpts";
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ti,cpts-ext-ts-inputs = <4>;
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ti,cpts-periodic-outputs = <2>;
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};
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ti,psil-config0 {
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linux,udma-mode = <UDMA_PKT_MODE>;
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statictr-type = <PSIL_STATIC_TR_NONE>;
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ti,needs-epib;
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ti,psd-size = <16>;
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};
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ti,psil-config1 {
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linux,udma-mode = <UDMA_PKT_MODE>;
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statictr-type = <PSIL_STATIC_TR_NONE>;
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ti,needs-epib;
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ti,psd-size = <16>;
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};
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ti,psil-config2 {
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linux,udma-mode = <UDMA_PKT_MODE>;
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statictr-type = <PSIL_STATIC_TR_NONE>;
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ti,needs-epib;
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ti,psd-size = <16>;
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};
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ti,psil-config3 {
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linux,udma-mode = <UDMA_PKT_MODE>;
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statictr-type = <PSIL_STATIC_TR_NONE>;
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ti,needs-epib;
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ti,psd-size = <16>;
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};
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ti,psil-config4 {
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linux,udma-mode = <UDMA_PKT_MODE>;
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statictr-type = <PSIL_STATIC_TR_NONE>;
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ti,needs-epib;
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ti,psd-size = <16>;
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};
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ti,psil-config5 {
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linux,udma-mode = <UDMA_PKT_MODE>;
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statictr-type = <PSIL_STATIC_TR_NONE>;
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ti,needs-epib;
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ti,psd-size = <16>;
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};
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ti,psil-config6 {
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linux,udma-mode = <UDMA_PKT_MODE>;
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statictr-type = <PSIL_STATIC_TR_NONE>;
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ti,needs-epib;
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ti,psd-size = <16>;
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};
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ti,psil-config7 {
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linux,udma-mode = <UDMA_PKT_MODE>;
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statictr-type = <PSIL_STATIC_TR_NONE>;
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ti,needs-epib;
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ti,psd-size = <16>;
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};
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};
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};
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&secure_proxy_main {
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u-boot,dm-spl;
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};
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&dmsc {
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u-boot,dm-spl;
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k3_sysreset: sysreset-controller {
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compatible = "ti,sci-sysreset";
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u-boot,dm-spl;
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};
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};
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&k3_pds {
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u-boot,dm-spl;
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};
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&k3_clks {
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u-boot,dm-spl;
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};
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&k3_reset {
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u-boot,dm-spl;
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};
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&wkup_pmx0 {
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u-boot,dm-spl;
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mcu_cpsw_pins_default: mcu_cpsw_pins_default {
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pinctrl-single,pins = <
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J721E_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* (N4) MCU_RGMII1_TX_CTL */
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J721E_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* (N5) MCU_RGMII1_RX_CTL */
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J721E_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* (M2) MCU_RGMII1_TD3 */
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J721E_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* (M3) MCU_RGMII1_TD2 */
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J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* (M4) MCU_RGMII1_TD1 */
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J721E_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* (M5) MCU_RGMII1_TD0 */
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J721E_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* (L2) MCU_RGMII1_RD3 */
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J721E_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* (L5) MCU_RGMII1_RD2 */
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J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* (M6) MCU_RGMII1_RD1 */
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J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* (L6) MCU_RGMII1_RD0 */
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J721E_WKUP_IOPAD(0x0070, PIN_INPUT, 0) /* (N1) MCU_RGMII1_TXC */
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J721E_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* (M1) MCU_RGMII1_RXC */
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>;
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};
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mcu_mdio_pins_default: mcu_mdio1_pins_default {
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pinctrl-single,pins = <
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J721E_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
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J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
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>;
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};
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};
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&main_pmx0 {
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u-boot,dm-spl;
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};
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&main_uart0 {
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u-boot,dm-spl;
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};
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&mcu_uart0 {
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u-boot,dm-spl;
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};
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&main_sdhci0 {
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u-boot,dm-spl;
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};
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&main_sdhci1 {
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u-boot,dm-spl;
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};
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&main_usbss0_pins_default {
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u-boot,dm-spl;
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};
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&usbss0 {
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u-boot,dm-spl;
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ti,usb2-only;
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};
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&usb0 {
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dr_mode = "peripheral";
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u-boot,dm-spl;
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};
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&mcu_cpsw {
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pinctrl-names = "default";
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pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
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};
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&davinci_mdio {
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phy0: ethernet-phy@0 {
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reg = <0>;
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ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
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ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
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};
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};
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&cpsw_port1 {
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phy-mode = "rgmii-rxid";
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phy-handle = <&phy0>;
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};
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&mcu_cpsw {
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reg = <0x0 0x46000000 0x0 0x200000>,
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<0x0 0x40f00200 0x0 0x2>;
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reg-names = "cpsw_nuss", "mac_efuse";
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cpsw-phy-sel@40f04040 {
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compatible = "ti,am654-cpsw-phy-sel";
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reg= <0x0 0x40f04040 0x0 0x4>;
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reg-names = "gmii-sel";
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};
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};
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