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![Peng Fan](/assets/img/avatar_default.png)
Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
189 lines
4.8 KiB
C
189 lines
4.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2018 NXP
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*
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*/
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#include <common.h>
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#include <errno.h>
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#include <asm/io.h>
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#include <asm/arch/ddr.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/ddr.h>
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#include <asm/arch/lpddr4_define.h>
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#include <asm/arch/sys_proto.h>
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void lpddr4_cfg_umctl2(struct dram_cfg_param *ddrc_cfg, int num)
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{
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int i = 0;
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for (i = 0; i < num; i++) {
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reg32_write(ddrc_cfg->reg, ddrc_cfg->val);
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ddrc_cfg++;
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}
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}
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void ddr_init(struct dram_timing_info *dram_timing)
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{
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unsigned int tmp;
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debug("DDRINFO: start lpddr4 ddr init\n");
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/* step 1: reset */
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if (is_imx8mq()) {
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reg32_write(SRC_DDRC_RCR_ADDR + 0x04, 0x8F00000F);
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reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00000F);
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reg32_write(SRC_DDRC_RCR_ADDR + 0x04, 0x8F000000);
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} else {
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reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00001F);
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reg32_write(SRC_DDRC_RCR_ADDR, 0x8F00000F);
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}
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mdelay(100);
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debug("DDRINFO: reset done\n");
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/*
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* change the clock source of dram_apb_clk_root:
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* source 4 800MHz /4 = 200MHz
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*/
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clock_set_target_val(DRAM_APB_CLK_ROOT, CLK_ROOT_ON |
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CLK_ROOT_SOURCE_SEL(4) |
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CLK_ROOT_PRE_DIV(CLK_ROOT_PRE_DIV4));
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/* disable iso */
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reg32_write(0x303A00EC, 0x0000ffff); /* PGC_CPU_MAPPING */
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reg32setbit(0x303A00F8, 5); /* PU_PGC_SW_PUP_REQ */
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debug("DDRINFO: cfg clk\n");
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dram_pll_init(MHZ(750));
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/*
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* release [0]ddr1_preset_n, [1]ddr1_core_reset_n,
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* [2]ddr1_phy_reset, [3]ddr1_phy_pwrokin_n
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*/
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reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000006);
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/*step2 Configure uMCTL2's registers */
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debug("DDRINFO: ddrc config start\n");
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lpddr4_cfg_umctl2(dram_timing->ddrc_cfg, dram_timing->ddrc_cfg_num);
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debug("DDRINFO: ddrc config done\n");
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/*
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* step3 de-assert all reset
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* RESET: <core_ddrc_rstn> DEASSERTED
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* RESET: <aresetn> for Port 0 DEASSERT(0)ED
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*/
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reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000004);
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reg32_write(SRC_DDRC_RCR_ADDR, 0x8F000000);
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reg32_write(DDRC_DBG1(0), 0x00000000);
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/* step4 */
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/* [0]dis_auto_refresh=1 */
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reg32_write(DDRC_RFSHCTL3(0), 0x00000011);
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/* [8]--1: lpddr4_sr allowed; [5]--1: software entry to SR */
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reg32_write(DDRC_PWRCTL(0), 0x000000a8);
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do {
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tmp = reg32_read(DDRC_STAT(0));
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} while ((tmp & 0x33f) != 0x223);
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reg32_write(DDRC_DDR_SS_GPR0, 0x01); /* LPDDR4 mode */
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/* step5 */
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reg32_write(DDRC_SWCTL(0), 0x00000000);
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/* step6 */
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tmp = reg32_read(DDRC_MSTR2(0));
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if (tmp == 0x2)
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reg32_write(DDRC_DFIMISC(0), 0x00000210);
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else if (tmp == 0x1)
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reg32_write(DDRC_DFIMISC(0), 0x00000110);
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else
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reg32_write(DDRC_DFIMISC(0), 0x00000010);
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/* step7 [0]--1: disable quasi-dynamic programming */
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reg32_write(DDRC_SWCTL(0), 0x00000001);
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/* step8 Configure LPDDR4 PHY's registers */
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debug("DDRINFO:ddrphy config start\n");
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ddr_cfg_phy(dram_timing);
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debug("DDRINFO: ddrphy config done\n");
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/*
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* step14 CalBusy.0 =1, indicates the calibrator is actively
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* calibrating. Wait Calibrating done.
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*/
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do {
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tmp = reg32_read(DDRPHY_CalBusy(0));
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} while ((tmp & 0x1));
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debug("DDRINFO:ddrphy calibration done\n");
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/* step15 [0]--0: to enable quasi-dynamic programming */
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reg32_write(DDRC_SWCTL(0), 0x00000000);
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/* step16 */
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tmp = reg32_read(DDRC_MSTR2(0));
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if (tmp == 0x2)
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reg32_write(DDRC_DFIMISC(0), 0x00000230);
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else if (tmp == 0x1)
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reg32_write(DDRC_DFIMISC(0), 0x00000130);
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else
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reg32_write(DDRC_DFIMISC(0), 0x00000030);
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/* step17 [0]--1: disable quasi-dynamic programming */
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reg32_write(DDRC_SWCTL(0), 0x00000001);
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/* step18 wait DFISTAT.dfi_init_complete to 1 */
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do {
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tmp = reg32_read(DDRC_DFISTAT(0));
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} while ((tmp & 0x1) == 0x0);
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/* step19 */
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reg32_write(DDRC_SWCTL(0), 0x00000000);
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/* step20~22 */
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tmp = reg32_read(DDRC_MSTR2(0));
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if (tmp == 0x2) {
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reg32_write(DDRC_DFIMISC(0), 0x00000210);
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/* set DFIMISC.dfi_init_complete_en again */
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reg32_write(DDRC_DFIMISC(0), 0x00000211);
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} else if (tmp == 0x1) {
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reg32_write(DDRC_DFIMISC(0), 0x00000110);
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/* set DFIMISC.dfi_init_complete_en again */
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reg32_write(DDRC_DFIMISC(0), 0x00000111);
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} else {
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/* clear DFIMISC.dfi_init_complete_en */
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reg32_write(DDRC_DFIMISC(0), 0x00000010);
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/* set DFIMISC.dfi_init_complete_en again */
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reg32_write(DDRC_DFIMISC(0), 0x00000011);
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}
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/* step23 [5]selfref_sw=0; */
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reg32_write(DDRC_PWRCTL(0), 0x00000008);
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/* step24 sw_done=1 */
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reg32_write(DDRC_SWCTL(0), 0x00000001);
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/* step25 wait SWSTAT.sw_done_ack to 1 */
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do {
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tmp = reg32_read(DDRC_SWSTAT(0));
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} while ((tmp & 0x1) == 0x0);
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#ifdef DFI_BUG_WR
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reg32_write(DDRC_DFIPHYMSTR(0), 0x00000001);
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#endif
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/* wait STAT.operating_mode([1:0] for ddr3) to normal state */
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do {
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tmp = reg32_read(DDRC_STAT(0));
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} while ((tmp & 0x3) != 0x1);
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/* step26 */
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reg32_write(DDRC_RFSHCTL3(0), 0x00000010);
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/* enable port 0 */
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reg32_write(DDRC_PCTRL_0(0), 0x00000001);
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debug("DDRINFO: ddrmix config done\n");
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/* save the dram timing config into memory */
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dram_config_save(dram_timing, CONFIG_SAVED_DRAM_TIMING_BASE);
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}
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