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![Peng Fan](/assets/img/avatar_default.png)
Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
171 lines
4.4 KiB
C
171 lines
4.4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2018 NXP
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*/
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#include <common.h>
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#include <spl.h>
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#include <asm/io.h>
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#include <errno.h>
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#include <asm/io.h>
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#include <asm/arch/ddr.h>
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#include <asm/arch/ddr.h>
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#include <asm/arch/lpddr4_define.h>
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#include <asm/sections.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define IMEM_LEN 32768 /* byte */
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#define DMEM_LEN 16384 /* byte */
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#define IMEM_2D_OFFSET 49152
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#define IMEM_OFFSET_ADDR 0x00050000
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#define DMEM_OFFSET_ADDR 0x00054000
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#define DDR_TRAIN_CODE_BASE_ADDR IP2APB_DDRPHY_IPS_BASE_ADDR(0)
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/* We need PHY iMEM PHY is 32KB padded */
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void ddr_load_train_firmware(enum fw_type type)
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{
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u32 tmp32, i;
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u32 error = 0;
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unsigned long pr_to32, pr_from32;
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unsigned long fw_offset = type ? IMEM_2D_OFFSET : 0;
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unsigned long imem_start = (unsigned long)&_end + fw_offset;
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unsigned long dmem_start = imem_start + IMEM_LEN;
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pr_from32 = imem_start;
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pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR;
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for (i = 0x0; i < IMEM_LEN; ) {
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tmp32 = readl(pr_from32);
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writew(tmp32 & 0x0000ffff, pr_to32);
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pr_to32 += 4;
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writew((tmp32 >> 16) & 0x0000ffff, pr_to32);
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pr_to32 += 4;
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pr_from32 += 4;
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i += 4;
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}
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pr_from32 = dmem_start;
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pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR;
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for (i = 0x0; i < DMEM_LEN; ) {
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tmp32 = readl(pr_from32);
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writew(tmp32 & 0x0000ffff, pr_to32);
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pr_to32 += 4;
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writew((tmp32 >> 16) & 0x0000ffff, pr_to32);
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pr_to32 += 4;
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pr_from32 += 4;
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i += 4;
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}
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debug("check ddr4_pmu_train_imem code\n");
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pr_from32 = imem_start;
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pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * IMEM_OFFSET_ADDR;
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for (i = 0x0; i < IMEM_LEN; ) {
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tmp32 = (readw(pr_to32) & 0x0000ffff);
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pr_to32 += 4;
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tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16);
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if (tmp32 != readl(pr_from32)) {
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debug("%lx %lx\n", pr_from32, pr_to32);
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error++;
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}
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pr_from32 += 4;
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pr_to32 += 4;
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i += 4;
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}
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if (error)
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printf("check ddr4_pmu_train_imem code fail=%d\n", error);
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else
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debug("check ddr4_pmu_train_imem code pass\n");
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debug("check ddr4_pmu_train_dmem code\n");
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pr_from32 = dmem_start;
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pr_to32 = DDR_TRAIN_CODE_BASE_ADDR + 4 * DMEM_OFFSET_ADDR;
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for (i = 0x0; i < DMEM_LEN;) {
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tmp32 = (readw(pr_to32) & 0x0000ffff);
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pr_to32 += 4;
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tmp32 += ((readw(pr_to32) & 0x0000ffff) << 16);
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if (tmp32 != readl(pr_from32)) {
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debug("%lx %lx\n", pr_from32, pr_to32);
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error++;
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}
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pr_from32 += 4;
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pr_to32 += 4;
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i += 4;
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}
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if (error)
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printf("check ddr4_pmu_train_dmem code fail=%d", error);
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else
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debug("check ddr4_pmu_train_dmem code pass\n");
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}
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void ddrphy_trained_csr_save(struct dram_cfg_param *ddrphy_csr,
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unsigned int num)
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{
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int i = 0;
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/* enable the ddrphy apb */
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dwc_ddrphy_apb_wr(0xd0000, 0x0);
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dwc_ddrphy_apb_wr(0xc0080, 0x3);
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for (i = 0; i < num; i++) {
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ddrphy_csr->val = dwc_ddrphy_apb_rd(ddrphy_csr->reg);
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ddrphy_csr++;
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}
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/* disable the ddrphy apb */
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dwc_ddrphy_apb_wr(0xc0080, 0x2);
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dwc_ddrphy_apb_wr(0xd0000, 0x1);
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}
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void dram_config_save(struct dram_timing_info *timing_info,
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unsigned long saved_timing_base)
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{
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int i = 0;
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struct dram_timing_info *saved_timing = (struct dram_timing_info *)saved_timing_base;
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struct dram_cfg_param *cfg;
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saved_timing->ddrc_cfg_num = timing_info->ddrc_cfg_num;
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saved_timing->ddrphy_cfg_num = timing_info->ddrphy_cfg_num;
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saved_timing->ddrphy_trained_csr_num = ddrphy_trained_csr_num;
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saved_timing->ddrphy_pie_num = timing_info->ddrphy_pie_num;
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/* save the fsp table */
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for (i = 0; i < 4; i++)
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saved_timing->fsp_table[i] = timing_info->fsp_table[i];
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cfg = (struct dram_cfg_param *)(saved_timing_base +
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sizeof(*timing_info));
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/* save ddrc config */
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saved_timing->ddrc_cfg = cfg;
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for (i = 0; i < timing_info->ddrc_cfg_num; i++) {
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cfg->reg = timing_info->ddrc_cfg[i].reg;
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cfg->val = timing_info->ddrc_cfg[i].val;
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cfg++;
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}
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/* save ddrphy config */
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saved_timing->ddrphy_cfg = cfg;
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for (i = 0; i < timing_info->ddrphy_cfg_num; i++) {
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cfg->reg = timing_info->ddrphy_cfg[i].reg;
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cfg->val = timing_info->ddrphy_cfg[i].val;
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cfg++;
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}
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/* save the ddrphy csr */
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saved_timing->ddrphy_trained_csr = cfg;
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for (i = 0; i < ddrphy_trained_csr_num; i++) {
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cfg->reg = ddrphy_trained_csr[i].reg;
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cfg->val = ddrphy_trained_csr[i].val;
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cfg++;
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}
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/* save the ddrphy pie */
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saved_timing->ddrphy_pie = cfg;
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for (i = 0; i < timing_info->ddrphy_pie_num; i++) {
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cfg->reg = timing_info->ddrphy_pie[i].reg;
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cfg->val = timing_info->ddrphy_pie[i].val;
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cfg++;
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}
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}
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