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https://github.com/brain-hackers/u-boot-brain
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![Simon Glass](/assets/img/avatar_default.png)
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
191 lines
3.9 KiB
C
191 lines
3.9 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2019 Linaro
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* Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
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*/
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#include <common.h>
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#include <cpu_func.h>
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#include <dm.h>
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#include <errno.h>
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#include <asm/cache.h>
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#include <init.h>
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#include <asm/io.h>
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#include <asm/arch/hi3660.h>
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#include <asm/armv8/mmu.h>
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#include <asm/psci.h>
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#include <linux/arm-smccc.h>
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#include <linux/delay.h>
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#include <linux/psci.h>
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#define PMIC_REG_TO_BUS_ADDR(x) (x << 2)
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#define PMIC_VSEL_MASK 0x7
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DECLARE_GLOBAL_DATA_PTR;
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#if !CONFIG_IS_ENABLED(OF_CONTROL)
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#include <dm/platform_data/serial_pl01x.h>
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static const struct pl01x_serial_platdata serial_platdata = {
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.base = HI3660_UART6_BASE,
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.type = TYPE_PL011,
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.clock = 19200000
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};
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U_BOOT_DEVICE(hikey960_serial0) = {
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.name = "serial_pl01x",
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.platdata = &serial_platdata,
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};
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#endif
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static struct mm_region hikey_mem_map[] = {
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{
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.virt = 0x0UL, /* DDR */
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.phys = 0x0UL,
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.size = 0xC0000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
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PTE_BLOCK_INNER_SHARE
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}, {
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.virt = 0xE0000000UL, /* Peripheral block */
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.phys = 0xE0000000UL,
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.size = 0x20000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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/* List terminator */
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0,
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}
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};
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struct mm_region *mem_map = hikey_mem_map;
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int board_early_init_f(void)
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{
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return 0;
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}
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int misc_init_r(void)
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{
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return 0;
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}
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int dram_init(void)
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{
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gd->ram_size = PHYS_SDRAM_1_SIZE;
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return 0;
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}
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int dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
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gd->bd->bi_dram[0].size = gd->ram_size;
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return 0;
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}
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void hikey960_sd_init(void)
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{
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u32 data;
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/* Enable FPLL0 */
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data = readl(SCTRL_SCFPLLCTRL0);
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data |= SCTRL_SCFPLLCTRL0_FPLL0_EN;
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writel(data, SCTRL_SCFPLLCTRL0);
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/* Configure LDO16 */
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data = readl(PMU_REG_BASE + PMIC_REG_TO_BUS_ADDR(0x79)) &
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PMIC_VSEL_MASK;
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data |= 6;
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writel(data, PMU_REG_BASE + PMIC_REG_TO_BUS_ADDR(0x79));
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data = readl(PMU_REG_BASE + PMIC_REG_TO_BUS_ADDR(0x78));
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data |= 2;
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writel(data, PMU_REG_BASE + PMIC_REG_TO_BUS_ADDR(0x78));
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udelay(100);
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/* Configure LDO9 */
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data = readl(PMU_REG_BASE + PMIC_REG_TO_BUS_ADDR(0x6b)) &
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PMIC_VSEL_MASK;
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data |= 5;
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writel(data, PMU_REG_BASE + PMIC_REG_TO_BUS_ADDR(0x6b));
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data = readl(PMU_REG_BASE + PMIC_REG_TO_BUS_ADDR(0x6a));
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data |= 2;
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writel(data, PMU_REG_BASE + PMIC_REG_TO_BUS_ADDR(0x6a));
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udelay(100);
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/* GPIO CD */
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writel(0, PINMUX4_SDDET);
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/* SD Pinconf */
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writel(15 << 4, PINCONF3_SDCLK);
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writel((1 << 0) | (8 << 4), PINCONF3_SDCMD);
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writel((1 << 0) | (8 << 4), PINCONF3_SDDATA0);
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writel((1 << 0) | (8 << 4), PINCONF3_SDDATA1);
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writel((1 << 0) | (8 << 4), PINCONF3_SDDATA2);
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writel((1 << 0) | (8 << 4), PINCONF3_SDDATA3);
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/* Set SD clock mux */
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do {
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data = readl(CRG_REG_BASE + 0xb8);
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data |= ((1 << 6) | (1 << 6 << 16) | (0 << 4) | (3 << 4 << 16));
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writel(data, CRG_REG_BASE + 0xb8);
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data = readl(CRG_REG_BASE + 0xb8);
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} while ((data & ((1 << 6) | (3 << 4))) != ((1 << 6) | (0 << 4)));
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/* Take SD out of reset */
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writel(1 << 18, CRG_PERRSTDIS4);
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do {
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data = readl(CRG_PERRSTSTAT4);
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} while ((data & (1 << 18)) == (1 << 18));
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/* Enable hclk_gate_sd */
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data = readl(CRG_REG_BASE + 0);
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data |= (1 << 30);
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writel(data, CRG_REG_BASE + 0);
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/* Enable clk_andgt_mmc */
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data = readl(CRG_REG_BASE + 0xf4);
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data |= ((1 << 3) | (1 << 3 << 16));
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writel(data, CRG_REG_BASE + 0xf4);
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/* Enable clk_gate_sd */
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data = readl(CRG_PEREN4);
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data |= (1 << 17);
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writel(data, CRG_PEREN4);
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do {
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data = readl(CRG_PERCLKEN4);
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} while ((data & (1 << 17)) != (1 << 17));
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}
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static void show_psci_version(void)
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{
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struct arm_smccc_res res;
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arm_smccc_smc(ARM_PSCI_0_2_FN_PSCI_VERSION, 0, 0, 0, 0, 0, 0, 0, &res);
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printf("PSCI: v%ld.%ld\n",
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PSCI_VERSION_MAJOR(res.a0),
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PSCI_VERSION_MINOR(res.a0));
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}
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int board_init(void)
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{
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/* Init SD */
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hikey960_sd_init();
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show_psci_version();
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return 0;
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}
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void reset_cpu(ulong addr)
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{
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psci_system_reset();
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}
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