mirror of
https://github.com/brain-hackers/u-boot-brain
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241 lines
5.3 KiB
C
241 lines
5.3 KiB
C
/*
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* (C) Copyright 2000-2005
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* (C) Copyright 2005-2007
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* Beijing UD Technology Co., Ltd., taihusupport@amcc.com
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/processor.h>
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#include <asm/io.h>
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#include <spi.h>
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#include <asm/gpio.h>
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extern int lcd_init(void);
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/*
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* board_early_init_f
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*/
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int board_early_init_f(void)
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{
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lcd_init();
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mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
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mtdcr(uicer, 0x00000000); /* disable all ints */
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mtdcr(uiccr, 0x00000000);
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mtdcr(uicpr, 0xFFFF7F00); /* set int polarities */
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mtdcr(uictr, 0x00000000); /* set int trigger levels */
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mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
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mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
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mtebc(pb3ap, CFG_EBC_PB3AP); /* memory bank 3 (CPLD_LCM) initialization */
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mtebc(pb3cr, CFG_EBC_PB3CR);
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/*
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* Configure CPC0_PCI to enable PerWE as output
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* and enable the internal PCI arbiter
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*/
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mtdcr(cpc0_pci, CPC0_PCI_SPE | CPC0_PCI_HOST_CFG_EN | CPC0_PCI_ARBIT_EN);
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return 0;
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}
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/*
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* Check Board Identity:
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*/
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int checkboard(void)
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{
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char *s = getenv("serial#");
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puts("Board: Taihu - AMCC PPC405EP Evaluation Board");
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if (s != NULL) {
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puts(", serial# ");
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puts(s);
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}
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putc('\n');
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return 0;
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}
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/*************************************************************************
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* long int initdram
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*
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************************************************************************/
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long int initdram(int board)
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{
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return CFG_SDRAM_SIZE_PER_BANK * CFG_SDRAM_BANKS; /* 128Mbytes */
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}
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static int do_sw_stat(cmd_tbl_t* cmd_tp, int flags, int argc, char *argv[])
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{
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char stat;
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int i;
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stat = in_8((u8 *) CPLD_REG0_ADDR);
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printf("SW2 status: ");
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for (i=0; i<4; i++) /* 4-position */
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printf("%d:%s ", i, stat & (0x08 >> i)?"on":"off");
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printf("\n");
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return 0;
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}
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U_BOOT_CMD (
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sw2_stat, 1, 1, do_sw_stat,
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"sw2_stat - show status of switch 2\n",
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NULL
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);
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static int do_led_ctl(cmd_tbl_t* cmd_tp, int flags, int argc, char *argv[])
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{
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int led_no;
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if (argc != 3) {
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printf("%s", cmd_tp->usage);
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return -1;
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}
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led_no = simple_strtoul(argv[1], NULL, 16);
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if (led_no != 1 && led_no != 2) {
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printf("%s", cmd_tp->usage);
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return -1;
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}
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if (strcmp(argv[2],"off") == 0x0) {
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if (led_no == 1)
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gpio_write_bit(30, 1);
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else
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gpio_write_bit(31, 1);
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} else if (strcmp(argv[2],"on") == 0x0) {
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if (led_no == 1)
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gpio_write_bit(30, 0);
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else
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gpio_write_bit(31, 0);
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} else {
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printf("%s", cmd_tp->usage);
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return -1;
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}
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return 0;
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}
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U_BOOT_CMD (
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led_ctl, 3, 1, do_led_ctl,
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"led_ctl - make led 1 or 2 on or off\n",
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"<led_no> <on/off> - make led <led_no> on/off,\n"
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"\tled_no is 1 or 2\t"
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);
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#define SPI_CS_GPIO0 0
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#define SPI_SCLK_GPIO14 14
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#define SPI_DIN_GPIO15 15
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#define SPI_DOUT_GPIO16 16
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void spi_scl(int bit)
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{
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gpio_write_bit(SPI_SCLK_GPIO14, bit);
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}
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void spi_sda(int bit)
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{
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gpio_write_bit(SPI_DOUT_GPIO16, bit);
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}
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unsigned char spi_read(void)
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{
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return (unsigned char)gpio_read_out_bit(SPI_DIN_GPIO15);
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}
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void taihu_spi_chipsel(int cs)
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{
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gpio_write_bit(SPI_CS_GPIO0, cs);
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}
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spi_chipsel_type spi_chipsel[]= {
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taihu_spi_chipsel
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};
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int spi_chipsel_cnt = sizeof(spi_chipsel) / sizeof(spi_chipsel[0]);
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#ifdef CONFIG_PCI
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static unsigned char int_lines[32] = {
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29, 30, 27, 28, 29, 30, 25, 27,
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29, 30, 27, 28, 29, 30, 27, 28,
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29, 30, 27, 28, 29, 30, 27, 28,
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29, 30, 27, 28, 29, 30, 27, 28};
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static void taihu_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
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{
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unsigned char int_line = int_lines[PCI_DEV(dev) & 31];
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pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
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}
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int pci_pre_init(struct pci_controller *hose)
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{
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hose->fixup_irq = taihu_pci_fixup_irq;
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return 1;
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}
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#endif /* CONFIG_PCI */
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#ifdef CFG_DRAM_TEST
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int testdram(void)
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{
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unsigned long *mem = (unsigned long *)0;
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const unsigned long kend = (1024 / sizeof(unsigned long));
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unsigned long k, n;
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unsigned long msr;
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unsigned long total_kbytes = CFG_SDRAM_SIZE_PER_BANK * CFG_SDRAM_BANKS / 1024;
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msr = mfmsr();
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mtmsr(msr & ~(MSR_EE));
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for (k = 0; k < total_kbytes ;
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++k, mem += (1024 / sizeof(unsigned long))) {
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if ((k & 1023) == 0)
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printf("%3d MB\r", k / 1024);
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memset(mem, 0xaaaaaaaa, 1024);
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for (n = 0; n < kend; ++n) {
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if (mem[n] != 0xaaaaaaaa) {
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printf("SDRAM test fails at: %08x\n",
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(uint) & mem[n]);
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return 1;
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}
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}
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memset(mem, 0x55555555, 1024);
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for (n = 0; n < kend; ++n) {
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if (mem[n] != 0x55555555) {
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printf("SDRAM test fails at: %08x\n",
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(uint) & mem[n]);
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return 1;
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}
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}
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}
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printf("SDRAM test passes\n");
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mtmsr(msr);
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return 0;
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}
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#endif /* CFG_DRAM_TEST */
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