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https://github.com/brain-hackers/u-boot-brain
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7656d3982a
Add a routine to program the timing parameters for DDR3-1333 DRAM chips connected to the H6 DRAM controller. The values were gathered from doing back-calculations from a register dump, trying to match them up with the official JEDEC DDDR3 spec. If in doubt, the register dump values were taken for now, but the JEDEC recommendation were added as a comment. Many thanks to Jernej for contributing fixes! Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
6 lines
260 B
Makefile
6 lines
260 B
Makefile
obj-$(CONFIG_SUNXI_DRAM_DDR3_1333) += ddr3_1333.o
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obj-$(CONFIG_SUNXI_DRAM_LPDDR3_STOCK) += lpddr3_stock.o
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obj-$(CONFIG_SUNXI_DRAM_DDR2_V3S) += ddr2_v3s.o
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obj-$(CONFIG_SUNXI_DRAM_H6_LPDDR3) += h6_lpddr3.o
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obj-$(CONFIG_SUNXI_DRAM_H6_DDR3_1333) += h6_ddr3_1333.o
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