mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-08 12:16:16 +09:00
f1df936445
This patch adds the DDR3 setup and training code taken from the Marvell U-Boot repository. This code used to be included as a binary (bin_hdr) into the Armada A38x boot image. Not linked with the main U-Boot. With this code addition and the serdes/PHY setup code, the Armada A38x support in mainline U-Boot is finally self-contained. So the complete image for booting can be built from mainline U-Boot. Without any additional external inclusion. Note: This code has undergone many hours (days!) of coding-style cleanup and refactoring. It still is not checkpatch clean though, I'm afraid. As the factoring of the code has so many levels of indentation that many lines are longer than 80 chars. Signed-off-by: Stefan Roese <sr@denx.de>
32 lines
876 B
C
32 lines
876 B
C
/*
|
|
* Copyright (C) Marvell International Ltd. and its affiliates
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0
|
|
*/
|
|
|
|
#ifndef _DDR3_TRAINING_IP_STATIC_H_
|
|
#define _DDR3_TRAINING_IP_STATIC_H_
|
|
|
|
#include "ddr3_training_ip_def.h"
|
|
#include "ddr3_training_ip.h"
|
|
|
|
struct trip_delay_element {
|
|
u32 dqs_delay; /* DQS delay (m_sec) */
|
|
u32 ck_delay; /* CK Delay (m_sec) */
|
|
};
|
|
|
|
struct hws_tip_static_config_info {
|
|
u32 silicon_delay;
|
|
struct trip_delay_element *package_trace_arr;
|
|
struct trip_delay_element *board_trace_arr;
|
|
};
|
|
|
|
int ddr3_tip_run_static_alg(u32 dev_num, enum hws_ddr_freq freq);
|
|
int ddr3_tip_init_static_config_db(
|
|
u32 dev_num, struct hws_tip_static_config_info *static_config_info);
|
|
int ddr3_tip_init_specific_reg_config(u32 dev_num,
|
|
struct reg_data *reg_config_arr);
|
|
int ddr3_tip_static_phy_init_controller(u32 dev_num);
|
|
|
|
#endif /* _DDR3_TRAINING_IP_STATIC_H_ */
|