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https://github.com/brain-hackers/u-boot-brain
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This general MMDC driver adds basic support for Freescale MMDC (Multi Mode DDR Controller). Currently MMDC is integrated on ARMv8 LS1012A SoC for DDR3L, there will be a update to this driver to support more flexible configuration if new features (DDR4, multiple controllers/chip selections, etc) are implimented in future. Meantime, reuse common MMDC driver for LS1012ARDB/LS1012AQDS/ LS1012AFRDM. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
37 lines
1.1 KiB
Makefile
37 lines
1.1 KiB
Makefile
#
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# Copyright 2008-2014 Freescale Semiconductor, Inc.
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#
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# SPDX-License-Identifier: GPL-2.0
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#
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obj-$(CONFIG_SYS_FSL_DDR1) += main.o util.o ctrl_regs.o options.o \
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lc_common_dimm_params.o
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obj-$(CONFIG_SYS_FSL_DDR2) += main.o util.o ctrl_regs.o options.o \
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lc_common_dimm_params.o
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obj-$(CONFIG_SYS_FSL_DDR3) += main.o util.o ctrl_regs.o options.o \
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lc_common_dimm_params.o
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obj-$(CONFIG_SYS_FSL_DDR4) += main.o util.o ctrl_regs.o options.o \
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lc_common_dimm_params.o
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ifdef CONFIG_DDR_SPD
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SPD := y
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endif
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ifdef CONFIG_SPD_EEPROM
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SPD := y
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endif
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ifdef SPD
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obj-$(CONFIG_SYS_FSL_DDR1) += ddr1_dimm_params.o
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obj-$(CONFIG_SYS_FSL_DDR2) += ddr2_dimm_params.o
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obj-$(CONFIG_SYS_FSL_DDR3) += ddr3_dimm_params.o
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obj-$(CONFIG_SYS_FSL_DDR4) += ddr4_dimm_params.o
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endif
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obj-$(CONFIG_FSL_DDR_INTERACTIVE) += interactive.o
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obj-$(CONFIG_SYS_FSL_DDRC_GEN1) += mpc85xx_ddr_gen1.o
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obj-$(CONFIG_SYS_FSL_DDRC_GEN2) += mpc85xx_ddr_gen2.o
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obj-$(CONFIG_SYS_FSL_DDRC_GEN3) += mpc85xx_ddr_gen3.o
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obj-$(CONFIG_SYS_FSL_DDR_86XX) += mpc86xx_ddr.o
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obj-$(CONFIG_SYS_FSL_DDRC_ARM_GEN3) += arm_ddr_gen3.o
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obj-$(CONFIG_SYS_FSL_DDRC_GEN4) += fsl_ddr_gen4.o
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obj-$(CONFIG_SYS_FSL_MMDC) += fsl_mmdc.o
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