York Sun 59a4089f82 corenet_ds: pick the middle value for all tested timing parameters ... For DDR3 controller, the clk_adjust and wrlvl_start are platform-dependent. The best values should be picked up from the middle of all working combinations. This patch updates the table with confirmed values tested on Hynix dual-rank UDIMMs (HMT125U7BFR8C-H9) at 1300MT/s, 1200MT/s, 1000MT/s, 900MT/s, 800MT/s and Kingston quad-rank RDIMMs (KVR1333D3Q8R9S/4G) at 1300MT/s, 1200MT/s, 1000MT/s. Signed-off-by: York Sun <yorksun@freescale.com>		2011-03-05 10:13:50 -06:00
..
corenet_ds.c	powerpc/8xxx: Refactor SRIO initialization into common code	2011-01-14 01:32:21 -06:00
ddr.c	corenet_ds: pick the middle value for all tested timing parameters	2011-03-05 10:13:50 -06:00
law.c	powerpc/p4080: Add support for the P4080DS board	2010-08-01 11:18:40 -05:00
Makefile	Switch from archive libraries to partial linking	2010-11-17 21:02:18 +01:00
p4080ds_ddr.c	Adding fixed sdram setting for cornet_ds board	2010-10-20 02:38:39 -05:00
pci.c	powerpc/85xx: Rework corenet_ds pci_init_board to use common FSL PCIe code	2011-01-14 01:32:21 -06:00
tlb.c	powerpc/p4080: Add support for the P4080DS board	2010-08-01 11:18:40 -05:00