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https://github.com/brain-hackers/u-boot-brain
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![John Rigby](/assets/img/avatar_default.png)
It can be optimised out by the compiler otherwise resulting in obscure errors like a board not booting. This has been documented in README since 2006 when these were first fixed up for GCC 4.x. Signed-off-by: John Rigby <john.rigby@linaro.org> Fix some additional places. Signed-off-by: Wolfgang Denk <wd@denx.de> Acked-By: Albert ARIBAUD <albert.aribaud@free.fr>
195 lines
4.8 KiB
C
195 lines
4.8 KiB
C
/*
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* U-boot - serial.c Blackfin Serial Driver
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*
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* Copyright (c) 2005-2008 Analog Devices Inc.
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*
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* Copyright (c) 2003 Bas Vermeulen <bas@buyways.nl>,
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* BuyWays B.V. (www.buyways.nl)
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*
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* Based heavily on:
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* blkfinserial.c: Serial driver for BlackFin DSP internal USRTs.
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* Copyright(c) 2003 Metrowerks <mwaddel@metrowerks.com>
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* Copyright(c) 2001 Tony Z. Kou <tonyko@arcturusnetworks.com>
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* Copyright(c) 2001-2002 Arcturus Networks Inc. <www.arcturusnetworks.com>
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*
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* Based on code from 68328 version serial driver imlpementation which was:
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* Copyright (C) 1995 David S. Miller <davem@caip.rutgers.edu>
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* Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>
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* Copyright (C) 1998, 1999 D. Jeff Dionne <jeff@uclinux.org>
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* Copyright (C) 1999 Vladimir Gurevich <vgurevic@cisco.com>
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*
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* (C) Copyright 2000-2004
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* Licensed under the GPL-2 or later.
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*/
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/* Anomaly notes:
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* 05000086 - we don't support autobaud
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* 05000099 - we only use DR bit, so losing others is not a problem
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* 05000100 - we don't use the UART_IIR register
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* 05000215 - we poll the uart (no dma/interrupts)
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* 05000225 - no workaround possible, but this shouldnt cause errors ...
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* 05000230 - we tweak the baud rate calculation slightly
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* 05000231 - we always use 1 stop bit
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* 05000309 - we always enable the uart before we modify it in anyway
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* 05000350 - we always enable the uart regardless of boot mode
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* 05000363 - we don't support break signals, so don't generate one
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*/
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#include <common.h>
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#include <watchdog.h>
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#include <asm/blackfin.h>
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#include <asm/mach-common/bits/uart.h>
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_UART_CONSOLE
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#include "serial.h"
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#ifdef CONFIG_DEBUG_SERIAL
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uint16_t cached_lsr[256];
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uint16_t cached_rbr[256];
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size_t cache_count;
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/* The LSR is read-to-clear on some parts, so we have to make sure status
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* bits aren't inadvertently lost when doing various tests. This also
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* works around anomaly 05000099 at the same time by keeping a cumulative
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* tally of all the status bits.
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*/
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static uint16_t uart_lsr_save;
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static uint16_t uart_lsr_read(void)
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{
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uint16_t lsr = bfin_read16(&pUART->lsr);
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uart_lsr_save |= (lsr & (OE|PE|FE|BI));
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return lsr | uart_lsr_save;
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}
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/* Just do the clear for everyone since it can't hurt. */
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static void uart_lsr_clear(void)
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{
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uart_lsr_save = 0;
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bfin_write16(&pUART->lsr, bfin_read16(&pUART->lsr) | -1);
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}
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#else
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/* When debugging is disabled, we only care about the DR bit, so if other
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* bits get set/cleared, we don't really care since we don't read them
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* anyways (and thus anomaly 05000099 is irrelevant).
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*/
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static uint16_t uart_lsr_read(void)
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{
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return bfin_read16(&pUART->lsr);
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}
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static void uart_lsr_clear(void)
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{
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bfin_write16(&pUART->lsr, bfin_read16(&pUART->lsr) | -1);
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}
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#endif
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/* Symbol for our assembly to call. */
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void serial_set_baud(uint32_t baud)
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{
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serial_early_set_baud(baud);
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}
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/* Symbol for common u-boot code to call.
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* Setup the baudrate (brg: baudrate generator).
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*/
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void serial_setbrg(void)
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{
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serial_set_baud(gd->baudrate);
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}
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/* Symbol for our assembly to call. */
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void serial_initialize(void)
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{
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serial_early_init();
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}
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/* Symbol for common u-boot code to call. */
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int serial_init(void)
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{
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serial_initialize();
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serial_setbrg();
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uart_lsr_clear();
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#ifdef CONFIG_DEBUG_SERIAL
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cache_count = 0;
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memset(cached_lsr, 0x00, sizeof(cached_lsr));
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memset(cached_rbr, 0x00, sizeof(cached_rbr));
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#endif
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return 0;
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}
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void serial_putc(const char c)
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{
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/* send a \r for compatibility */
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if (c == '\n')
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serial_putc('\r');
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WATCHDOG_RESET();
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/* wait for the hardware fifo to clear up */
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while (!(uart_lsr_read() & THRE))
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continue;
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/* queue the character for transmission */
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bfin_write16(&pUART->thr, c);
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SSYNC();
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WATCHDOG_RESET();
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}
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int serial_tstc(void)
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{
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WATCHDOG_RESET();
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return (uart_lsr_read() & DR) ? 1 : 0;
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}
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int serial_getc(void)
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{
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uint16_t uart_rbr_val;
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/* wait for data ! */
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while (!serial_tstc())
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continue;
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/* grab the new byte */
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uart_rbr_val = bfin_read16(&pUART->rbr);
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#ifdef CONFIG_DEBUG_SERIAL
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/* grab & clear the LSR */
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uint16_t uart_lsr_val = uart_lsr_read();
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cached_lsr[cache_count] = uart_lsr_val;
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cached_rbr[cache_count] = uart_rbr_val;
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cache_count = (cache_count + 1) % ARRAY_SIZE(cached_lsr);
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if (uart_lsr_val & (OE|PE|FE|BI)) {
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uint16_t dll, dlh;
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printf("\n[SERIAL ERROR]\n");
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ACCESS_LATCH();
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dll = bfin_read16(&pUART->dll);
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dlh = bfin_read16(&pUART->dlh);
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ACCESS_PORT_IER();
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printf("\tDLL=0x%x DLH=0x%x\n", dll, dlh);
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do {
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--cache_count;
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printf("\t%3i: RBR=0x%02x LSR=0x%02x\n", cache_count,
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cached_rbr[cache_count], cached_lsr[cache_count]);
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} while (cache_count > 0);
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return -1;
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}
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#endif
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uart_lsr_clear();
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return uart_rbr_val;
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}
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void serial_puts(const char *s)
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{
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while (*s)
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serial_putc(*s++);
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}
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#endif
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