mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-07 03:36:16 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
111 lines
2.5 KiB
C
111 lines
2.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2000-2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*/
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#include <config.h>
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#include <common.h>
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#include <asm/immap.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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int checkboard(void)
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{
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puts("Board: ");
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puts("Freescale M5235 EVB\n");
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return 0;
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};
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int dram_init(void)
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{
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sdram_t *sdram = (sdram_t *)(MMAP_SDRAM);
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gpio_t *gpio = (gpio_t *)(MMAP_GPIO);
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u32 dramsize, i, dramclk;
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/*
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* When booting from external Flash, the port-size is less than
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* the port-size of SDRAM. In this case it is necessary to enable
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* Data[15:0] on Port Address/Data.
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*/
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out_8(&gpio->par_ad,
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GPIO_PAR_AD_ADDR23 | GPIO_PAR_AD_ADDR22 | GPIO_PAR_AD_ADDR21 |
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GPIO_PAR_AD_DATAL);
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/* Initialize PAR to enable SDRAM signals */
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out_8(&gpio->par_sdram,
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GPIO_PAR_SDRAM_SDWE | GPIO_PAR_SDRAM_SCAS |
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GPIO_PAR_SDRAM_SRAS | GPIO_PAR_SDRAM_SCKE |
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GPIO_PAR_SDRAM_SDCS(3));
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dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
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for (i = 0x13; i < 0x20; i++) {
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if (dramsize == (1 << i))
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break;
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}
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i--;
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if (!(in_be32(&sdram->dacr0) & SDRAMC_DARCn_RE)) {
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dramclk = gd->bus_clk / (CONFIG_SYS_HZ * CONFIG_SYS_HZ);
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/* Initialize DRAM Control Register: DCR */
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out_be16(&sdram->dcr, SDRAMC_DCR_RTIM_9CLKS |
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SDRAMC_DCR_RTIM_6CLKS |
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SDRAMC_DCR_RC((15 * dramclk) >> 4));
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/* Initialize DACR0 */
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out_be32(&sdram->dacr0,
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SDRAMC_DARCn_BA(CONFIG_SYS_SDRAM_BASE) |
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SDRAMC_DARCn_CASL_C1 | SDRAMC_DARCn_CBM_CMD20 |
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SDRAMC_DARCn_PS_32);
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asm("nop");
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/* Initialize DMR0 */
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out_be32(&sdram->dmr0,
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((dramsize - 1) & 0xFFFC0000) | SDRAMC_DMRn_V);
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asm("nop");
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/* Set IP (bit 3) in DACR */
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setbits_be32(&sdram->dacr0, SDRAMC_DARCn_IP);
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/* Wait 30ns to allow banks to precharge */
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for (i = 0; i < 5; i++) {
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asm("nop");
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}
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/* Write to this block to initiate precharge */
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*(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xA5A59696;
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/* Set RE (bit 15) in DACR */
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setbits_be32(&sdram->dacr0, SDRAMC_DARCn_RE);
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/* Wait for at least 8 auto refresh cycles to occur */
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for (i = 0; i < 0x2000; i++) {
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asm("nop");
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}
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/* Finish the configuration by issuing the MRS. */
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setbits_be32(&sdram->dacr0, SDRAMC_DARCn_IMRS);
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asm("nop");
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/* Write to the SDRAM Mode Register */
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*(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696;
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}
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gd->ram_size = dramsize;
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return 0;
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};
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int testdram(void)
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{
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/* TODO: XXX XXX XXX */
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printf("DRAM test not implemented!\n");
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return (0);
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}
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