Kumar Gala 58e5e9aff1 FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code. ... The main purpose of this rewrite it to be able to share the same initialization code on all FSL PowerPC products that have DDR controllers. (83xx, 85xx, 86xx). The code is broken up into the following steps: GET_SPD COMPUTE_DIMM_PARMS COMPUTE_COMMON_PARMS GATHER_OPTS ASSIGN_ADDRESSES COMPUTE_REGS PROGRAM_REGS This allows us to share more code an easily allow for board specific code overrides. Additionally this code base adds support for >4G of DDR and provides a foundation for supporting interleaving on processors with more than one controller. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Becky Bruce <becky.bruce@freescale.com> Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>		2008-08-27 02:05:58 +02:00
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cache.S	Clean up usage of icache_disable/dcache_disable	2008-08-19 00:57:28 +02:00
config.mk	PPC: Use r2 instead of r29 as global data pointer	2008-02-14 22:43:22 +01:00
cpu_init.c	POWERPC 86xx: Move BAT setup code to C	2008-08-11 23:53:59 +02:00
cpu.c	Merge commit 'wd/master'	2008-07-10 12:05:32 -05:00
fdt.c	fdt: rework fdt_fixup_ethernet() to use env instead of bd_t	2008-08-21 02:07:43 +02:00
interrupts.c	Feed the watchdog in u-boot for 8610 board.	2008-07-07 11:29:48 -05:00
Makefile	FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code.	2008-08-27 02:05:58 +02:00
spd_sdram.c	85xx/86xx: Move to dynamic mgmt of LAWs	2008-06-11 01:52:23 -05:00
speed.c	Fix calculation of I2C clock for some 86xx chips	2008-04-30 22:52:35 +02:00
start.S	POWERPC 86xx: Move BAT setup code to C	2008-08-11 23:53:59 +02:00
traps.c	Fix some more print() format errors.	2008-07-11 01:16:00 +02:00