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3d23287828
I/O APIC registers are addressed indirectly. Add io_apic_read() and io_apic_write() routines to help register access. Two macros for I/O APIC ID and version register offset are also added. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
43 lines
899 B
C
43 lines
899 B
C
/*
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* From coreboot file of the same name
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*
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* Copyright (C) 2010 coresystems GmbH
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef __ASM_IOAPIC_H
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#define __ASM_IOAPIC_H
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#define IO_APIC_ADDR 0xfec00000
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/* Direct addressed register */
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#define IO_APIC_INDEX (IO_APIC_ADDR + 0x00)
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#define IO_APIC_DATA (IO_APIC_ADDR + 0x10)
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/* Indirect addressed register offset */
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#define IO_APIC_ID 0x00
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#define IO_APIC_VER 0x01
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/**
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* io_apic_read() - Read I/O APIC register
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*
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* This routine reads I/O APIC indirect addressed register.
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*
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* @reg: address of indirect addressed register
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* @return: register value to read
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*/
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u32 io_apic_read(u32 reg);
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/**
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* io_apic_write() - Write I/O APIC register
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*
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* This routine writes I/O APIC indirect addressed register.
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*
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* @reg: address of indirect addressed register
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* @val: register value to write
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*/
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void io_apic_write(u32 reg, u32 val);
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#endif
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