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4a34e4b86f
The correct GPIOBASE address on the baytrail is 0x48 Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
14 lines
295 B
C
14 lines
295 B
C
/*
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* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _X86_ARCH_GPIO_H_
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#define _X86_ARCH_GPIO_H_
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/* Where in config space is the register that points to the GPIO registers? */
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#define PCI_CFG_GPIOBASE 0x48
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#endif /* _X86_ARCH_GPIO_H_ */
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