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https://github.com/brain-hackers/u-boot-brain
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e13afeef6f
The 2/3 usb-phys on the sunxi SoCs are really a single separate functional block, and are modelled as such in devicetree. So once we've moved all the sunxi usb code to the driver-model then phy_probe will be called once for the entire block from the driver-model enumeration code. Move to this now as this also avoids problems with phy_probe being called multiple times once we introduce ohci support. This also allows us to get rid of the sunxi_usb_phy_enabled_count variable as phy_probe now is guaranteed to be called only once. Since we're effectively rewriting the probe / remove functions, move them to the end of the file while we are at it, as that is the most logical place for them. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
67 lines
1.7 KiB
C
67 lines
1.7 KiB
C
/*
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* Sunxi ehci glue
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*
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* Copyright (C) 2015 Hans de Goede <hdegoede@redhat.com>
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* Copyright (C) 2014 Roman Byshko <rbyshko@gmail.com>
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*
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* Based on code from
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* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/usb_phy.h>
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#include <asm/io.h>
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#include "ehci.h"
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int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr,
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struct ehci_hcor **hcor)
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{
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struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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int ahb_gate_offset;
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ahb_gate_offset = index ? AHB_GATE_OFFSET_USB_EHCI1 :
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AHB_GATE_OFFSET_USB_EHCI0;
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setbits_le32(&ccm->ahb_gate0, 1 << ahb_gate_offset);
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#ifdef CONFIG_SUNXI_GEN_SUN6I
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setbits_le32(&ccm->ahb_reset0_cfg, 1 << ahb_gate_offset);
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#endif
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sunxi_usb_phy_init(index + 1);
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sunxi_usb_phy_power_on(index + 1);
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if (index == 0)
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*hccr = (void *)SUNXI_USB1_BASE;
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else
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*hccr = (void *)SUNXI_USB2_BASE;
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*hcor = (struct ehci_hcor *)((uint32_t) *hccr
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+ HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
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debug("sunxi-ehci: init hccr %x and hcor %x hc_length %d\n",
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(uint32_t)*hccr, (uint32_t)*hcor,
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(uint32_t)HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
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return 0;
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}
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int ehci_hcd_stop(int index)
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{
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struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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int ahb_gate_offset;
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sunxi_usb_phy_power_off(index + 1);
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sunxi_usb_phy_exit(index + 1);
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ahb_gate_offset = index ? AHB_GATE_OFFSET_USB_EHCI1 :
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AHB_GATE_OFFSET_USB_EHCI0;
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#ifdef CONFIG_SUNXI_GEN_SUN6I
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clrbits_le32(&ccm->ahb_reset0_cfg, 1 << ahb_gate_offset);
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#endif
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clrbits_le32(&ccm->ahb_gate0, 1 << ahb_gate_offset);
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return 0;
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}
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