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90d7cc42b3
Due to incorrect placement of the clock gate cell in the ldb_di[x]_clk tree, the glitchy parent mux of ldb_di[x]_clk can cause a glitch to enter the ldb_di_ipu_div divider. If the divider gets locked up, no ldb_di[x]_clk is generated, and the LVDS display will hang when the ipu_di_clk is sourced from ldb_di_clk. To fix the problem, both the new and current parent of the ldb_di_clk should be disabled before the switch. This patch ensures that correct steps are followed when ldb_di_clk parent is switched in the beginning of boot. This patch was ported from the 3.10.17 NXP kernel http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/commit/?h=imx_3.10.17_1.0.1_ga&id=eecbe9a52587cf9eec30132fb9b8a6761f3a1e6d NXP errata number: ERR009219, EB821 Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com>
83 lines
1.8 KiB
C
83 lines
1.8 KiB
C
/*
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* (C) Copyright 2009
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* Stefano Babic, DENX Software Engineering, sbabic@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ASM_ARCH_CLOCK_H
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#define __ASM_ARCH_CLOCK_H
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#include <common.h>
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#ifdef CONFIG_SYS_MX6_HCLK
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#define MXC_HCLK CONFIG_SYS_MX6_HCLK
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#else
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#define MXC_HCLK 24000000
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#endif
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#ifdef CONFIG_SYS_MX6_CLK32
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#define MXC_CLK32 CONFIG_SYS_MX6_CLK32
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#else
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#define MXC_CLK32 32768
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#endif
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enum mxc_clock {
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MXC_ARM_CLK = 0,
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MXC_PER_CLK,
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MXC_AHB_CLK,
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MXC_IPG_CLK,
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MXC_IPG_PERCLK,
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MXC_UART_CLK,
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MXC_CSPI_CLK,
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MXC_AXI_CLK,
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MXC_EMI_SLOW_CLK,
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MXC_DDR_CLK,
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MXC_ESDHC_CLK,
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MXC_ESDHC2_CLK,
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MXC_ESDHC3_CLK,
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MXC_ESDHC4_CLK,
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MXC_SATA_CLK,
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MXC_NFC_CLK,
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MXC_I2C_CLK,
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};
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enum ldb_di_clock {
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MXC_PLL5_CLK = 0,
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MXC_PLL2_PFD0_CLK,
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MXC_PLL2_PFD2_CLK,
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MXC_MMDC_CH1_CLK,
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MXC_PLL3_SW_CLK,
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};
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enum enet_freq {
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ENET_25MHZ,
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ENET_50MHZ,
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ENET_100MHZ,
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ENET_125MHZ,
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};
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u32 imx_get_uartclk(void);
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u32 imx_get_fecclk(void);
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unsigned int mxc_get_clock(enum mxc_clock clk);
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void setup_gpmi_io_clk(u32 cfg);
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void hab_caam_clock_enable(unsigned char enable);
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void enable_ocotp_clk(unsigned char enable);
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void enable_usboh3_clk(unsigned char enable);
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void enable_uart_clk(unsigned char enable);
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int enable_usdhc_clk(unsigned char enable, unsigned bus_num);
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int enable_sata_clock(void);
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void disable_sata_clock(void);
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int enable_pcie_clock(void);
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int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
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int enable_spi_clk(unsigned char enable, unsigned spi_num);
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void enable_ipu_clock(void);
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int enable_fec_anatop_clock(int fec_id, enum enet_freq freq);
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void enable_enet_clk(unsigned char enable);
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int enable_lcdif_clock(u32 base_addr);
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void enable_qspi_clk(int qspi_num);
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void enable_thermal_clk(void);
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void mxs_set_lcdclk(u32 base_addr, u32 freq);
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void select_ldb_di_clock_source(enum ldb_di_clock clk);
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#endif /* __ASM_ARCH_CLOCK_H */
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