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https://github.com/brain-hackers/u-boot-brain
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d60a2099a2
The QorIQ LS1 family is built on Layerscape architecture, the industry's first software-aware, core-agnostic networking architecture to offer unprecedented efficiency and scale. Freescale LS102xA is a set of SoCs combines two ARM Cortex-A7 cores that have been optimized for high reliability and pack the highest level of integration available for sub-3 W embedded communications processors with Layerscape architecture and with a comprehensive enablement model focused on ease of programmability. Signed-off-by: Alison Wang <alison.wang@freescale.com> Signed-off-by: Jason Jin <jason.jin@freescale.com> Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
54 lines
687 B
C
54 lines
687 B
C
/*
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* Copyright 2014 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*
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*/
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#ifndef __ASM_ARCH_IMX_REGS_H__
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#define __ASM_ARCH_IMX_REGS_H__
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#define I2C_QUIRK_REG /* enable 8-bit driver */
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#ifdef CONFIG_LPUART_32B_REG
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struct lpuart_fsl {
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u32 baud;
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u32 stat;
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u32 ctrl;
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u32 data;
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u32 match;
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u32 modir;
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u32 fifo;
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u32 water;
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};
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#else
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struct lpuart_fsl {
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u8 ubdh;
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u8 ubdl;
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u8 uc1;
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u8 uc2;
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u8 us1;
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u8 us2;
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u8 uc3;
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u8 ud;
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u8 uma1;
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u8 uma2;
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u8 uc4;
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u8 uc5;
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u8 ued;
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u8 umodem;
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u8 uir;
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u8 reserved;
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u8 upfifo;
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u8 ucfifo;
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u8 usfifo;
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u8 utwfifo;
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u8 utcfifo;
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u8 urwfifo;
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u8 urcfifo;
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u8 rsvd[28];
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};
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#endif
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#endif /* __ASM_ARCH_IMX_REGS_H__ */
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