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https://github.com/brain-hackers/u-boot-brain
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d60a2099a2
The QorIQ LS1 family is built on Layerscape architecture, the industry's first software-aware, core-agnostic networking architecture to offer unprecedented efficiency and scale. Freescale LS102xA is a set of SoCs combines two ARM Cortex-A7 cores that have been optimized for high reliability and pack the highest level of integration available for sub-3 W embedded communications processors with Layerscape architecture and with a comprehensive enablement model focused on ease of programmability. Signed-off-by: Alison Wang <alison.wang@freescale.com> Signed-off-by: Jason Jin <jason.jin@freescale.com> Signed-off-by: Jingchang Lu <jingchang.lu@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
34 lines
580 B
C
34 lines
580 B
C
/*
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* Copyright 2014 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __FSL_SERDES_H
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#define __FSL_SERDES_H
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#include <config.h>
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enum srds_prtcl {
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NONE = 0,
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PCIE1,
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PCIE2,
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SATA1,
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SGMII_TSEC1,
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SGMII_TSEC2,
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};
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enum srds {
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FSL_SRDS_1 = 0,
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FSL_SRDS_2 = 1,
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};
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int is_serdes_configured(enum srds_prtcl device);
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void fsl_serdes_init(void);
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const char *serdes_clock_to_string(u32 clock);
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int serdes_get_first_lane(u32 sd, enum srds_prtcl device);
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enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane);
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#endif /* __FSL_SERDES_H */
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