mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
5750e5e29a
Intel Quark SoC has a low end x86 processor with only 400MHz frequency. Currently it takes about 15 seconds for U-Boot to boot to shell and the most time consuming part is with MRC, which is about 12 seconds. MRC programs lots of registers on the SoC internal message bus indirectly accessed via pci bus. To speed up the boot, create an optimized version of pci config read/write dword routines which directly operate on PCI I/O ports. These two routines are inlined to provide better performance too. Now it only takes about 3 seconds to finish MRC, which is really fast (4 times faster than before). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
78 lines
2.0 KiB
C
78 lines
2.0 KiB
C
/*
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* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/device.h>
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#include <asm/arch/msg_port.h>
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#include <asm/arch/quark.h>
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void msg_port_setup(int op, int port, int reg)
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{
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qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_REG,
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(((op) << 24) | ((port) << 16) |
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(((reg) << 8) & 0xff00) | MSG_BYTE_ENABLE));
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}
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u32 msg_port_read(u8 port, u32 reg)
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{
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u32 value;
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qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
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reg & 0xffffff00);
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msg_port_setup(MSG_OP_READ, port, reg);
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qrk_pci_read_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, &value);
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return value;
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}
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void msg_port_write(u8 port, u32 reg, u32 value)
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{
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qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, value);
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qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
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reg & 0xffffff00);
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msg_port_setup(MSG_OP_WRITE, port, reg);
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}
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u32 msg_port_alt_read(u8 port, u32 reg)
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{
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u32 value;
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qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
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reg & 0xffffff00);
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msg_port_setup(MSG_OP_ALT_READ, port, reg);
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qrk_pci_read_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, &value);
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return value;
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}
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void msg_port_alt_write(u8 port, u32 reg, u32 value)
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{
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qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, value);
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qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
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reg & 0xffffff00);
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msg_port_setup(MSG_OP_ALT_WRITE, port, reg);
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}
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u32 msg_port_io_read(u8 port, u32 reg)
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{
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u32 value;
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qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
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reg & 0xffffff00);
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msg_port_setup(MSG_OP_IO_READ, port, reg);
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qrk_pci_read_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, &value);
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return value;
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}
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void msg_port_io_write(u8 port, u32 reg, u32 value)
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{
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qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, value);
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qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
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reg & 0xffffff00);
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msg_port_setup(MSG_OP_IO_WRITE, port, reg);
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}
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