mirror of
https://github.com/brain-hackers/u-boot-brain
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aff2523f69
Memory Type Range Registers are used to tell the CPU whether memory is cacheable and if so the cache write mode to use. Clean up the existing header file to follow style, and remove the unneeded code. These can speed up booting so should be supported. Add these to global_data so they can be requested while booting. We will apply the changes during relocation (in a later commit). Signed-off-by: Simon Glass <sjg@chromium.org>
96 lines
2.1 KiB
C
96 lines
2.1 KiB
C
/*
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* (C) Copyright 2002-2010
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __ASM_GBL_DATA_H
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#define __ASM_GBL_DATA_H
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#ifndef __ASSEMBLY__
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enum pei_boot_mode_t {
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PEI_BOOT_NONE = 0,
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PEI_BOOT_SOFT_RESET,
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PEI_BOOT_RESUME,
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};
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struct memory_area {
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uint64_t start;
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uint64_t size;
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};
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struct memory_info {
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int num_areas;
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uint64_t total_memory;
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uint64_t total_32bit_memory;
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struct memory_area area[CONFIG_NR_DRAM_BANKS];
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};
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#define MAX_MTRR_REQUESTS 8
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/**
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* A request for a memory region to be set up in a particular way. These
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* requests are processed before board_init_r() is called. They are generally
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* optional and can be ignored with some performance impact.
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*/
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struct mtrr_request {
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int type; /* MTRR_TYPE_... */
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uint64_t start;
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uint64_t size;
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};
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/* Architecture-specific global data */
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struct arch_global_data {
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struct global_data *gd_addr; /* Location of Global Data */
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uint8_t x86; /* CPU family */
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uint8_t x86_vendor; /* CPU vendor */
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uint8_t x86_model;
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uint8_t x86_mask;
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uint32_t x86_device;
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uint64_t tsc_base; /* Initial value returned by rdtsc() */
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uint32_t tsc_base_kclocks; /* Initial tsc as a kclocks value */
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uint32_t tsc_prev; /* For show_boot_progress() */
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uint32_t tsc_mhz; /* TSC frequency in MHz */
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void *new_fdt; /* Relocated FDT */
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uint32_t bist; /* Built-in self test value */
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enum pei_boot_mode_t pei_boot_mode;
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const struct pch_gpio_map *gpio_map; /* board GPIO map */
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struct memory_info meminfo; /* Memory information */
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#ifdef CONFIG_HAVE_FSP
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void *hob_list; /* FSP HOB list */
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#endif
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struct mtrr_request mtrr_req[MAX_MTRR_REQUESTS];
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int mtrr_req_count;
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};
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#endif
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#include <asm-generic/global_data.h>
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#ifndef __ASSEMBLY__
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static inline __attribute__((no_instrument_function)) gd_t *get_fs_gd_ptr(void)
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{
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gd_t *gd_ptr;
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asm volatile("fs movl 0, %0\n" : "=r" (gd_ptr));
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return gd_ptr;
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}
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#define gd get_fs_gd_ptr()
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#endif
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/*
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* Our private Global Data Flags
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*/
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#define GD_FLG_COLD_BOOT 0x00100 /* Cold Boot */
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#define GD_FLG_WARM_BOOT 0x00200 /* Warm Boot */
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#define DECLARE_GLOBAL_DATA_PTR
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#endif /* __ASM_GBL_DATA_H */
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