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https://github.com/brain-hackers/u-boot-brain
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3d1988ab47
This patch re-formats the arm920t s3c24x0 nand driver in preparation for changes to add support for the Embest SBC2440-II Board. The changes are as follows: - re-indent the code using Lindent - make sure register layouts are defined using a C struct - replace the upper-case typedef'ed C struct names with lower case non-typedef'ed ones - make sure registers are accessed using the proper accessor functions - run checkpatch.pl and fix any error reports It assumes the following patch has been applied first: - [U-Boot][PATCH-ARM] CONFIG_SYS_HZ fix for ARM902T S3C24X0 Boards, 05/09/2009 - patches 1/4, 2/4 and 3/4 of this series Tested on an Embest SBC2440-II Board with local u-boot patches as I don't have any s3c2400 or s3c2410 boards but need this patch applying before I can submit patches for the SBC2440-II Board. Also, temporarily modified sbc2410x, smdk2400, smdk2410 and trab configs to use the mtd nand driver (which isn't used by any board at the moment), ran MAKEALL for all ARM9 targets and no new warnings or errors were found. Signed-off-by: Kevin Morfitt <kevin.morfitt@fearnside-systems.co.uk> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
160 lines
4.3 KiB
C
160 lines
4.3 KiB
C
/*
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* (C) Copyright 2006 OpenMoko, Inc.
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* Author: Harald Welte <laforge@openmoko.org>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <nand.h>
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#include <s3c2410.h>
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#include <asm/io.h>
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#define S3C2410_NFCONF_EN (1<<15)
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#define S3C2410_NFCONF_512BYTE (1<<14)
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#define S3C2410_NFCONF_4STEP (1<<13)
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#define S3C2410_NFCONF_INITECC (1<<12)
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#define S3C2410_NFCONF_nFCE (1<<11)
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#define S3C2410_NFCONF_TACLS(x) ((x)<<8)
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#define S3C2410_NFCONF_TWRPH0(x) ((x)<<4)
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#define S3C2410_NFCONF_TWRPH1(x) ((x)<<0)
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#define S3C2410_ADDR_NALE 4
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#define S3C2410_ADDR_NCLE 8
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static void s3c2410_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
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{
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struct nand_chip *chip = mtd->priv;
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struct s3c2410_nand *nand = s3c2410_get_base_nand();
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debugX(1, "hwcontrol(): 0x%02x 0x%02x\n", cmd, ctrl);
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if (ctrl & NAND_CTRL_CHANGE) {
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ulong IO_ADDR_W = (ulong)nand;
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if (!(ctrl & NAND_CLE))
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IO_ADDR_W |= S3C2410_ADDR_NCLE;
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if (!(ctrl & NAND_ALE))
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IO_ADDR_W |= S3C2410_ADDR_NALE;
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chip->IO_ADDR_W = (void *)IO_ADDR_W;
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if (ctrl & NAND_NCE)
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writel(readl(&nand->NFCONF) & ~S3C2410_NFCONF_nFCE,
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&nand->NFCONF);
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else
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writel(readl(&nand->NFCONF) | S3C2410_NFCONF_nFCE,
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&nand->NFCONF);
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}
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if (cmd != NAND_CMD_NONE)
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writeb(cmd, chip->IO_ADDR_W);
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}
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static int s3c2410_dev_ready(struct mtd_info *mtd)
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{
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struct s3c2410_nand *nand = s3c2410_get_base_nand();
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debugX(1, "dev_ready\n");
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return readl(&nand->NFSTAT) & 0x01;
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}
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#ifdef CONFIG_S3C2410_NAND_HWECC
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void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode)
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{
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struct s3c2410_nand *nand = s3c2410_get_base_nand();
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debugX(1, "s3c2410_nand_enable_hwecc(%p, %d)\n", mtd, mode);
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writel(readl(&nand->NFCONF) | S3C2410_NFCONF_INITECC, &nand->NFCONF);
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}
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static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
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u_char *ecc_code)
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{
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ecc_code[0] = NFECC0;
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ecc_code[1] = NFECC1;
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ecc_code[2] = NFECC2;
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debugX(1, "s3c2410_nand_calculate_hwecc(%p,): 0x%02x 0x%02x 0x%02x\n",
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mtd , ecc_code[0], ecc_code[1], ecc_code[2]);
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return 0;
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}
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static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat,
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u_char *read_ecc, u_char *calc_ecc)
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{
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if (read_ecc[0] == calc_ecc[0] &&
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read_ecc[1] == calc_ecc[1] &&
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read_ecc[2] == calc_ecc[2])
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return 0;
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printf("s3c2410_nand_correct_data: not implemented\n");
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return -1;
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}
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#endif
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int board_nand_init(struct nand_chip *nand)
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{
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u_int32_t cfg;
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u_int8_t tacls, twrph0, twrph1;
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struct s3c24x0_clock_power *clk_power = s3c24x0_get_base_clock_power();
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struct s3c2410_nand *nand_reg = s3c2410_get_base_nand();
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debugX(1, "board_nand_init()\n");
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writel(readl(&clk_power->CLKCON) | (1 << 4), &clk_power->CLKCON);
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/* initialize hardware */
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twrph0 = 3;
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twrph1 = 0;
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tacls = 0;
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cfg = S3C2410_NFCONF_EN;
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cfg |= S3C2410_NFCONF_TACLS(tacls - 1);
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cfg |= S3C2410_NFCONF_TWRPH0(twrph0 - 1);
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cfg |= S3C2410_NFCONF_TWRPH1(twrph1 - 1);
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writel(cfg, &nand_reg->NFCONF);
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/* initialize nand_chip data structure */
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nand->IO_ADDR_R = nand->IO_ADDR_W = (void *)&nand_reg->NFDATA;
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/* read_buf and write_buf are default */
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/* read_byte and write_byte are default */
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/* hwcontrol always must be implemented */
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nand->cmd_ctrl = s3c2410_hwcontrol;
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nand->dev_ready = s3c2410_dev_ready;
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#ifdef CONFIG_S3C2410_NAND_HWECC
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nand->ecc.hwctl = s3c2410_nand_enable_hwecc;
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nand->ecc.calculate = s3c2410_nand_calculate_ecc;
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nand->ecc.correct = s3c2410_nand_correct_data;
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nand->ecc.mode = NAND_ECC_HW3_512;
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#else
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nand->ecc.mode = NAND_ECC_SOFT;
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#endif
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#ifdef CONFIG_S3C2410_NAND_BBT
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nand->options = NAND_USE_FLASH_BBT;
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#else
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nand->options = 0;
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#endif
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debugX(1, "end of nand_init\n");
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return 0;
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}
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